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| ASAHI KASEI [AK4538] AK4538 16Bit CODEC with MIC/HP/SPK-AMP GENERAL DESCRIPTION The AK4538 targeted at PDA and other low-power, small size applications. It features a 16-bit stereo CODEC with a built-in Microphone-Amplifier, Headphone-Amplifier and Speaker-Amplifier. Input circuits include a Microphone-Amplifier and an ALC (Auto Level Control) circuit. The AK4538 is available in a 52-QFN, utilizing less board space than competitive offerings. FEATURES 1. Resolution : 16bits 2. Recording Function * 1ch Mono Input * 1st MIC Amplifier : +20dB or 0dB * 2nd Amplifier with ALC : +27.5dB -8dB, 0.5dB Step * ADC Performance : S/(N+D) : 79dB, DR, S/N : 83dB 3. Playback Function * Digital De-emphasis Filter (tc=50/15s, fs=32kHz, 44.1kHz, 48kHz) * Digital Volume (0dB -127dB, 0.5dB Step, Mute) * Stereo Line Output - Performance : S/(N+D) : 88dB, S/N : 92dB * Headphone-Amp - S/(N+D) : 70dB, S/N : 90dB - Output Power : 15mW@16 (HVDD=3.3V) * Mono Speaker-Amp with ALC - S/(N+D) : 64dB, S/N : 90dB - BTL Output - Output Power : 300mW@8 (HVDD=3.3V) * Mono and Stereo Beep Inputs * AUX Input * Mono Output 4. Power Management 5. Master Clock (1) PLL Mode * Frequencies : 11.2896MHz, 12MHz and 12.288MHz * Input Level : CMOS (2) External Clock Mode * Frequencies : 1.792MHz 12.288MHz 6. Output Master Clock Frequencies : 32fs/64fs/128fs/256fs 7. Sampling Rate (1) PLL Mode * 8kHz, 11.025kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz, 48kHz (2) External Clock Mode * 7kHz 48kHz 8. Control mode: 4-wire Serial / I2C Bus 9. Master/Slave mode MS0198-E-01 -1- 2003/5 ASAHI KASEI [AK4538] 10. Audio Interface Format : MSB First, 2's compliment * ADC : I2S, 16bit MSB justified * DAC : I2S, 16bit MSB justified, 16bit LSB justified 11. Ta = -10 70C 12. Power Supply: 2.4V 3.6V (typ. 3.3V) 13. Power Supply Current * AVDD+DVDD : 17mA * PVDD : 1.2mA * HVDD (HP-AMP=ON, SPK-AMP=OFF) : 6.5mA * HVDD (HP-AMP=OFF, SPK-AMP=ON) : 9mA 14. Package : 52pin QFN 15. AK4534 Pin Compatible n Block Diagram M/S MICOUT PMMIC AVSS AVDD AIN MPE MIC Pow er Supply CAD0 MPI INT MIC-AMP 0dB or 20dB MIC Pow er Supply ALC1 (IPGA) PMADC ADC EXT MDT 0.075 x AVDD PMMO HPF PDN ATT ATT Audio Interface LRCK BICK MOUT+ ATT MOUTPMLO PMDAC SDTO SDTI LOUT DAC ROUT HVDD HVSS HPL PMHPL MIX PMMIX DATT SMUTE I2C DSP and uP CSN/CAD1 Control Register CCLK/SCL CDTI/SDA CDTO HP-AMP MIX PMHPR MIX PMPLL XTO HPR MUTET HP-AMP MIX PLL XTI/MCKI PVDD PMSPK SPP SPKAMP SPN ALC2 MIX MIX Volume PVSS MCKO PMBPS PMBPM PMAUX MOUT VCOC VCOM BEEPL DVSS DVDD BEEPR BEEPM MIN MOUT2 AUXIN+ AUXIN- Figure 1. Block Diagram MS0198-E-01 -2- 2003/5 ASAHI KASEI [AK4538] n Ordering Guide AK4538VN AKD4538 -10 +70C 52pin QFN (0.4mm pitch) Evaluation board for AK4538 n Pin Layout (52pin QFN) AUXIN+ BEEPM BEEPR MOUT+ MOUT2 AUXIN- BEEPL MOUT- ROUT LOUT 52 51 50 49 48 47 46 45 44 43 42 41 40 MICOUT MDT EXT MPE MPI INT VCOM AVSS AVDD PVDD PVSS VCOC NC 1 2 3 4 5 6 7 8 9 10 11 12 39 38 37 36 35 34 33 32 31 30 29 28 MUTET HPL HPR HVSS HVDD SPN SPP M/S XTI/MCKI XTO DVSS DVDD NC AK4538VN Top View 13 27 14 15 16 17 18 19 20 21 22 23 24 25 26 CSN/CAD1 CCLK/SCL CDTI/SDA MCKO CDTO SDTO CAD0 LRCK BICK SDTI PDN I2C MS0198-E-01 -3- NC MIN AIN NC 2003/5 ASAHI KASEI [AK4538] PIN/FUNCTION of 52QFN No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 Pin Name MICOUT MDT EXT MPE MPI INT VCOM AVSS AVDD PVDD PVSS VCOC NC CAD0 PDN CSN CAD1 CCLK SCL CDTI SDA CDTO I2C SDTI SDTO LRCK BICK MCKO NC I/O O I I O O I O O I I I I I I I I/O O I I O I/O I/O O Function Microphone Analog Output Pin Microphone Detect Pin (Internal pull down by 500k) External Microphone Input Pin (Mono Input) MIC Power Supply Pin for External Microphone MIC Power Supply Pin for Internal Microphone Internal Microphone Input Pin (Mono Input) Common Voltage Output Pin, 0.45 x AVDD Bias voltage of ADC inputs and DAC outputs. Analog Ground Pin Analog Power Supply Pin PLL Power Supply Pin PLL Ground Pin Output Pin for Loop Filter of PLL Circuit This pin should be connected to PVSS with one resistor and capacitor in series. No Connect. No internal bonding. Chip Address 0 Select Pin Power-Down Mode Pin "H": Power up, "L": Power down reset and initializes the control register. Chip Select Pin (I2C = "L") Chip Address 1 Select Pin (I2C = "H") Control Data Clock Pin (I2C = "L") Control Data Clock Pin (I2C = "H") Control Data Input Pin (I2C = "L") Control Data Input Pin (I2C = "H") Control Data Output Pin (I2C = "L") Control Mode Select Pin "H": I2C Bus, "L": 4-wire Serial Audio Serial Data Input Pin Audio Serial Data Output Pin Input / Output Channel Clock Pin Audio Serial Data Clock Pin Master Clock Output Pin No Connect. No internal bonding. MS0198-E-01 -4- 2003/5 ASAHI KASEI [AK4538] No. 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 Pin Name NC DVDD DVSS XTO XTI MCKI M/S SPP SPN HVDD HVSS HPR HPL MUTET MIN MOUT2 ROUT LOUT MOUTMOUT+ AUXINAUXIN+ BEEPM BEEPR BEEPL AIN NC I/O O I I I O O O O O I O O O O O I I I I I I - Function No Connect. No internal bonding. Digital Power Supply Pin Digital Ground Pin X'tal Output Pin X'tal Input Pin External Master Clock Input Pin Master / Slave Mode Pin "H" : Master Mode, "L" : Slave Mode Speaker Amp Positive Output Pin Speaker Amp Negative Output Pin Headphone Amp Power Supply Pin Headphone Amp Ground Pin Rch Headphone Amp Output Pin Lch Headphone Amp Output Pin Mute Time Constant Control Pin Connected to HVSS pin with a capacitor for mute time constant. ALC Input Pin Analog Mixing Output Pin Line Out Right Channel Line Out Left Channel Mono Line Negative Output Pin Mono Line Positive Output Pin Mono AUX Negative Input Pin Mono AUX Positive Input Pin Mono Beep Signal Input Pin Rch Stereo Beep Signal Input Pin Lch Stereo Beep Signal Input Pin Analog Input Pin No Connect. No internal bonding. Note: All input pins except analog input pins (INT, EXT, AIN, MIN, AUXIN+, AUXIN-, BEEPM, BEEPL, and BEEPR) should not be left floating. MS0198-E-01 -5- 2003/5 ASAHI KASEI [AK4538] ABSOLUTE MAXIMUM RATINGS (AVSS, DVSS, PVSS, HVSS=0V; Note 1) Parameter Power Supplies: Analog Digital PLL Headphone-Amp / Speaker-Amp |AVSS - PVSS| (Note 2) |AVSS - DVSS| (Note 2) |AVSS - HVSS| (Note 2) Input Current, Any Pin Except Supplies Analog Input Voltage Digital Input Voltage Ambient Temperature (powered applied) Storage Temperature Symbol AVDD DVDD PVDD HVDD GND1 GND2 GND3 IIN VINA VIND Ta Tstg min -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -10 -65 max 4.6 4.6 4.6 4.6 0.3 0.3 0.3 10 AVDD+0.3 DVDD+0.3 70 150 Units V V V V V V V mA V V C C Note 1. All voltages with respect to ground. Note 2. AVSS, DVSS, PVSS and HVSS must be connected to the same analog ground plane. WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. RECOMMENDED OPERATING CONDITIONS (AVSS, DVSS, PVSS, HVSS=0V; Note 1) Parameter Power Supplies Analog (Note 3) Digital PLL HP / SPK-Amp Symbol AVDD DVDD PVDD HVDD min 2.4 2.4 2.4 2.4 typ 3.3 3.3 3.3 3.3 max 3.6 AVDD AVDD AVDD Units V V V V Note 1. All voltages with respect to ground. Note 3. The power up sequence between AVDD, DVDD, HVDD and PVDD is not critical. It is recommended that DVDD and PVDD are the same voltage as AVDD in order to reduce the current at power down mode. * AKM assumes no responsibility for the usage beyond the conditions in this datasheet. MS0198-E-01 -6- 2003/5 ASAHI KASEI [AK4538] ANALOG CHARACTERISTICS (Ta=25C; AVDD=DVDD=PVDD=HVDD=3.3V; AVSS=DVSS=PVSS=HVSS=0V; fs=44.1kHz, BICK=64fs; Signal Frequency=1kHz; 16bit Data; Measurement frequency=20Hz 20kHz; unless otherwise specified) Parameter min typ max Units MIC Amplifier Input Resistance 20 30 40 k Gain (MGAIN bit = "0") 0 dB (MGAIN bit = "1") 20 dB MIC Power Supply Output Voltage (Note 4) 2.22 2.47 2.72 V Output Current 1.25 mA MIC Detection 0.247 0.165 mV Comparator Voltage Level (Note 5) 750 250 500 Internal pull down Resistance k Input PGA Characteristics: Input Resistance (Note 6) 5 10 15 k Step Size 0.1 0.5 0.9 dB Gain Control Range +27.5 dB -8 ADC Analog Input Characteristics: MIC Gain=20dB, IPGA=0dB, ALC1=OFF, MIC IPGA ADC Resolution 16 Bits Input Voltage (MIC Gain=20dB, Note 7) 0.168 0.198 0.228 Vpp 71 79 dB S/(N+D) (-1dBFS) 75 83 dB D-Range (-60dBFS, A-weighted) S/N (A-weighted) 75 83 dB DAC Characteristics: Resolution 16 Bits Stereo Line Output Characteristics: RL=10k, DAC LOUT/ROUT 1.94 Output Voltage (Note 8) 1.74 2.14 Vpp S/(N+D) (-3dBFS) 78 88 dBFS 85 92 dB S/N (A-weighted) 0.1 0.5 dB Interchannel Gain Mismatch Load Resistance 10 k 30 pF Load Capacitance Mono Line Output Characteristics: RL=20k, DAC MOUT+/MOUTOutput Voltage (Note 9) MOGN=1, -17dB 0.31 Vpp 3.56 3.96 4.36 MOGN=0, +6dB Vpp 76 S/(N+D) (-3dBFS) MOGN=1, -17dB dBFS 79 89 MOGN=0, +6dB dBFS 79 S/N (A-weighted) MOGN=1, -17dB dB 85 95 MOGN=0, +6dB dB Load Resistance MOGN=1, -17dB 2 k MOGN=0, +6dB 20 k 30 pF Load Capacitance Note 4. Output voltage is proportional to AVDD voltage. Vout = 0.75 x AVDD. Note 5. Comparator Voltage Level is proportional to AVDD voltage. Vout = 0.05 x AVDD(min), 0.075 x AVDD(max). Note 6. When IPGA Gain is changed, this typical value changes between 8k and 11k. Note 7. Input voltage is proportional to AVDD voltage. Vin = 0.06 x AVDD. Note 8. Output voltage is proportional to AVDD voltage. Vout = 0.588 x AVDD. Note 9. Output voltage is proportional to AVDD voltage. Vout = 1.2 x AVDD(typ)@MOGN=0, 0.094 x AVDD(typ)@MOGN=1 at Full-differential output. Vout = 0.6 x AVDD(typ)@MOGN=0, 0.047 x AVDD(typ) @MOGN=1 at Single-end Output. MS0198-E-01 -7- 2003/5 ASAHI KASEI [AK4538] Parameter min typ max Headphone-Amp Characteristics: RL=22.8, DAC HPL/HPR, DATT=0dB 1.54 1.92 2.30 Output Voltage (Note 10) 60 70 S/(N+D) (-3dBFS) S/N (A-weighted) 80 90 70 85 Interchannel Isolation 0.1 0.5 Interchannel Gain Mismatch 20 Load Resistance Load Capacitance (C1 of Figure 2) 30 300 (C2 of Figure 2) Speaker-Amp Characteristics: RL=8, BTL, DAC MOUT2 MIN SPP/SPN, ALC2=OFF Output Voltage (Note 11) 2.37 2.96 3.55 S/(N+D) 50 64 82 90 S/N (A-weighted) Load Resistance 8 30 Load Capacitance AUX Input: AUXIN+, AUXIN- pin 1.98 Maximum Input Voltage (Note 12) 25 40 55 Input Resistance Step Size 1 3 5 Gain Control Range +24 -21 BEEP Input: BEEPL, BEEPR, BEEPM pin 1.98 Maximum Input Voltage (Note 13) 14 20 26 Feedback Resistance Mono Input: MIN pin 1.98 Maximum Input Voltage (Note 14) 12 24 36 Input Resistance (Note 15) Mono Output: RL=10k, DAC MIX MOUT2 1.94 Output Voltage (Note 16) Load Resistance 10 30 Load Capacitance (Note 17) Units Vpp dBFS dB dB dB pF pF Vpp dB dB pF Vpp k dB dB Vpp k Vpp k Vpp k pF Note 10. Output voltage is proportional to AVDD voltage. Vout = 0.582 x AVDD. Note 11. Output voltage is proportional to HVDD voltage. Vout = 0.897 x AVDD at Full-differential output. Note 12. Maximum Input Voltage is proportional to AVDD voltage. Vin = 0.6 x AVDD. Note 13. Maximum Input Voltage is proportional to AVDD voltage. Vin = 0.6 x AVDD.BEEP-AMP can't output more than this maximum voltage. Note 14. Maximum Input Voltage is proportional to AVDD voltage. Vin = 0.6 x AVDD. Note 15. When ALC2 Gain is changed, this typical value changes between 22k and 26k. Note 16. Output Voltage is proportional to AVDD voltage. Vout = 0.588 x AVDD. Note 17. When the output pin drives a capacitive load, a resistor should be added in series between the output pin and capacitive load. HP-Amp HPL/HPR pin 47F > 6.8 C1 C2 16 Figure 2. Headphone-amp output circuit MS0198-E-01 -8- 2003/5 ASAHI KASEI [AK4538] Parameter Power Supplies Power Up (PDN = "H") AVDD+DVDD (Note 18) PVDD HVDD: HP-AMP Normal Operation No Output (Note 19) HVDD: SPK-AMP Normal Operation No Output (Note 20) Power Down (PDN = "L") (Note 21) AVDD+DVDD PVDD HVDD min typ max Units 17 1.2 6.5 9 10 10 10 26 2 10 18 100 100 100 mA mA mA mA A A A Note 18. PMMIC=PMADC=PMDAC=PMMO=PMSPK=PMHPL=PMHPR=PMVCM=PMPLL=PMXTL=PMBPM =PMBPS=PMLO=PMAUX= "1",MCKO= "1" and Master Mode. AVDD : 11mA (typ.), DVDD : 6mA (typ.) AVDD : 11mA (typ.), DVDD : 4mA (typ.) at MCKO= "0" in Slave Mode Note 19. PMMIC=PMADC=PMDAC=PMMO=PMHPL=PMHPR=PMVCM=PMPLL=PMXTL=PMBPM =PMBPS=PMLO=PMAUX= "1", PMSPK= "0". Note 20. PMMIC=PMADC=PMDAC=PMMO=PMSPK=PMVCM=PMPLL=PMXTL=PMBPM=PMBPS=PMLO =PMAUX= "1", PMHPL=PMHPR= "0". Note 21. All digital input pins are fixed to DVDD or DVSS. MS0198-E-01 -9- 2003/5 ASAHI KASEI [AK4538] FILTER CHARACTERISTICS (Ta=-10 70C; AVDD, DVDD, PVDD, HVDD=2.4 3.6V; fs=44.1kHz; DEM=OFF) Parameter Symbol min typ ADC Digital Filter (Decimation LPF): Passband (Note 22) 0.1dB PB 0 -1.0dB 20.0 -3.0dB 21.1 Stopband SB 27.0 Passband Ripple PR Stopband Attenuation SA 65 Group Delay (Note 23) GD 17.0 Group Delay Distortion GD 0 ADC Digital Filter (HPF): Frequency Response -3.0dB FR 3.4 (Note 22) -0.5dB 10 -0.1dB 22 DAC Digital Filter: Passband (Note 22) 0.1dB PB 0 -6.0dB 22.05 Stopband SB 24.1 Passband Ripple PR Stopband Attenuation SA 43 Group Delay (Note 23) GD 16.8 DAC Digital Filter + SCF: Frequency Response: 0 20.0kHz FR 0.5 BOOST Filter: (Note 24) 5.74 FR Frequency Response MIN 20Hz 2.92 100Hz 0.0 1kHz 5.94 FR MID 20Hz 4.71 100Hz 0.14 1kHz 16.04 FR MAX 20Hz 10.55 100Hz 0.3 1kHz max 17.4 0.1 Units kHz kHz kHz kHz dB dB 1/fs s Hz Hz Hz 20.0 0.06 kHz kHz kHz dB dB 1/fs dB dB dB dB dB dB dB dB dB dB Note 22. The passband and stopband frequencies scale with fs (system sampling rate). For example, ADC is PB=0.454*fs (@-1.0dB), DAC is PB=0.454*fs (@-0.01dB). Note 23. The calculated delay time caused by digital filtering. This time is from the input of analog signal to setting of the 16-bit data of both channels from the input register to the output register of the ADC. This time includes the group delay of the HPF. For the DAC, this time is from setting the 16-bit data of both channels from the input register to the output of analog signal. Note 24. These frequency responses scale with fs. If a high-level and low frequency signal is input, the analog output clips to the full-scale. MS0198-E-01 - 10 - 2003/5 ASAHI KASEI [AK4538] DC CHARACTERISTICS (Ta=-10 70C; AVDD, DVDD, PVDD, HVDD=2.4 3.6V) Parameter Symbol VIH High-Level Input Voltage VIL Low-Level Input Voltage VAC Input Voltage at AC Coupling (Note 25) VOH High-Level Output Voltage (Iout=-200A) Low-Level Output Voltage VOL (Except SDA pin: Iout=200A) VOL ( SDA pin: Iout= 3mA) Input Leakage Current Iin Note 25. When AC coupled capacitor is connected to MCKI pin. min 70%DVDD 50%DVDD DVDD-0.2 typ Max 30%DVDD 0.2 0.4 10 Units V V V V V V A SWITCHING CHARACTERISTICS (Ta=-10 70C; AVDD, DVDD, PVDD, HVDD=2.4 3.6V; CL=20pF) Parameter Symbol min Master Clock Timing Crystal Resonator Frequency External Clock Frequency Pulse Width Low Pulse Width High AC Pulse Width (Note 26) MCKO Output Frequency Duty Cycle : except fs=32kHz fs=32kHz at 256fs (Note 27) LRCK Frequency Frequency Duty Cycle Slave mode Master mode Audio Interface Timing Slave mode BICK Period BICK Pulse Width Low Pulse Width High LRCK Edge to BICK "" (Note 28) BICK "" to LRCK Edge (Note 28) LRCK to SDTO (MSB) (Except I2S mode) BICK "" to SDTO SDTI Hold Time SDTI Setup Time Master mode BICK Frequency BICK Duty BICK "" to LRCK BICK "" to SDTO SDTI Hold Time SDTI Setup Time 11.2896 1.792 0.4/fCLK 0.4/fCLK 0.4/fCLK 0.224 40 typ max 12.288 12.288 Units MHz MHz ns ns ns MHz % % kHz % % fCLK tCLKL tCLKH tACW fMCK dMCK dMCK fs Duty Duty 50 33 12.288 60 7 45 50 48 55 tBCK tBCKL tBCKH tLRB tBLR tLRS tBSD tSDH tSDS fBCK dBCK tMBLR tBSD tSDH tSDS 312.5 130 130 50 50 80 80 50 50 64fs 50 80 80 ns ns ns ns ns ns ns ns ns Hz % ns ns ns ns -80 -80 50 50 Note 26. Pulse width to ground level when MCKI is connected to a capacitor in series and a resistor is connected to ground. (Refer to Figure 4) Note 27. PMPLL bit = "1". Note 28. BICK rising edge must not occur at the same time as LRCK edge. MS0198-E-01 - 11 - 2003/5 ASAHI KASEI [AK4538] Parameter Control Interface Timing (4-wire Serial mode): CCLK Period CCLK Pulse Width Low Pulse Width High CDTI Setup Time CDTI Hold Time CSN "H" Time CSN "" to CCLK "" CCLK "" to CSN "" CDTO Delay CSN "" to CDTO Hi-Z Control Interface Timing (I2C Bus mode): SCL Clock Frequency Bus Free Time Between Transmissions Start Condition Hold Time (prior to first clock pulse) Clock Low Time Clock High Time Setup Time for Repeated Start Condition SDA Hold Time from SCL Falling (Note 29) SDA Setup Time from SCL Rising Rise Time of Both SDA and SCL Lines Fall Time of Both SDA and SCL Lines Setup Time for Stop Condition Pulse Width of Spike Noise Suppressed by Input Filter Reset Timing PDN Pulse Width PMADC "" to SDTO valid (Note 30) (Note 31) Symbol tCCK tCCKL tCCKH tCDS tCDH tCSW tCSS tCSH tDCD tCCZ fSCL tBUF tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tR tF tSU:STO tSP tPD tPDV min 200 80 80 40 40 150 50 50 typ max Units ns ns ns ns ns ns ns ns ns ns kHz s s s s s s s s s s ns ns 1/fs 50 70 4.7 4.0 4.7 4.0 4.7 0 0.25 4.0 0 150 2081 100 1.0 0.3 50 Note 29. Data must be held long enough to bridge the 300ns-transition time of SCL. Note 30. The AK4538 can be reset by the PDN pin = "L". Note 31. This is the count of LRCK "" from the PMADC bit = "1". Purchase of Asahi Kasei Microsystems Co., Ltd I C components conveys a license under the Philips I C 2 2 patent to use the components in the I C system, provided the system conform to the I C specifications defined by Philips. 2 2 MS0198-E-01 - 12 - 2003/5 ASAHI KASEI [AK4538] n Timing Diagram 1/fCLK VIH MCLK tCLKH 1/fs VIH LRCK VIL tBCK VIH VIL tBCKH fMCK tBCKL tCLKL VIL BICK MCKO dMCK dMCK Figure 3. Clock Timing 1/fCLK 50%DVDD 1000pF MCKI Input 100k AGND Measurement Point AGND tACW tACW VAC Figure 4. MCKI AC Coupling Timing MS0198-E-01 - 13 - 2003/5 ASAHI KASEI [AK4538] VIH LRCK VIL tBLR tLRB VIH BICK VIL tLRS tBSD SDTO tSDS tSDH 50%DVDD VIH SDTI VIL Figure 5. Audio Interface Timing (Slave mode) VIH LRCK VIL tMBLR dBCK 50%DVDD BICK tBSD SDTO tSDS tSDH 50%DVDD VIH SDTI VIL Figure 6. Audio Interface Timing (Master mode) MS0198-E-01 - 14 - 2003/5 ASAHI KASEI [AK4538] VIH CSN VIL tCSS tCCKL tCCKH VIH CCLK VIL tCDS CDTI C1 C0 tCDH VIH R/W VIL Hi-Z Figure 7. WRITE/READ Command Input Timing CDTO tCSW VIH CSN VIL tCSH VIH CCLK VIL VIH CDTI D2 D1 D0 VIL Hi-Z CDTO Figure 8. WRITE Data Input Timing MS0198-E-01 - 15 - 2003/5 ASAHI KASEI [AK4538] VIH CSN VIL VIH CCLK VIL VIH CDTI A1 A0 VIL tDCD CDTO Hi-Z D7 D6 50%DVDD Figure 9. READ Data Output Timing 1 tCSW VIH CSN VIL tCSH VIH CCLK VIL VIH CDTI VIL tCCZ Hi-Z CDTO D2 D1 D0 50%DVDD Figure 10. READ Data Output Timing 2 MS0198-E-01 - 16 - 2003/5 ASAHI KASEI [AK4538] SDA tBUF tLOW tR tHIGH tF tSP VIH VIL VIH SCL VIL tHD:STA Stop Start 2 tHD:DAT tSU:DAT tSU:STA Start tSU:STO Stop Figure 11. I C Bus Mode Timing VIH CSN VIL tPDV SDTO 50%DVDD tPD PDN VIL Figure 12. Power Down & Reset Timing MS0198-E-01 - 17 - 2003/5 ASAHI KASEI [AK4538] OPERATION OVERVIEW n Master Clock Source The AK4538 requires a master clock (MCLK). This master clock is input to the AK4538 by connecting a X'tal oscillator to XTI and XTO pins or by inputting an external CMOS-level clock to the XTI pin or by inputting an external clock that is greater than 50% of the DVDD level to the XTI pin through a capacitor. When using a X'tal oscillator, there should be capacitors between XTI/XTO pins and DVSS. When using an external clock, there are two choices: direct, where an external clock is input directly to the XTI pin and indirect, where the external clock is input through a capacitor. Master Clock X'tal Oscillator Status PMXTL bit (Figure 13) Oscillator ON 1 Oscillator OFF 0 External Clock Direct Input (Figure 14) Clock is input to MCKI pin. 0 MCKI pin is fixed to "L". 0 MCKI pin is fixed to "H". 0 MCKI pin is Hi-Z 0 AC Coupling Input (Figure 15) Clock is input to MCKI pin. 1 Clock isn't input to MCKI pin. 0 Table 1. Master Clock Status by PMXTL bit and MCKPD bit (1) X'tal Oscillator MCKPD bit 0 1 0 0/1 0 1 0 1 XTI MCKIPD= "0" C 25k C PMXTL = "1" XTO AK4538 Figure 13. X'tal mode - Note: The capacitor values depend on the X'tal oscillator used. (C : typ. 10 30pF) MS0198-E-01 - 18 - 2003/5 ASAHI KASEI [AK4538] (2) External Clock Direct Input XTI External Clock MCKPD = "0" 25k PMXTL = "0" XTO AK4538 Figure 14. External Clock mode (Input : CMOS Level) - Note: This clock level must not exceed DVDD level. (3) AC Coupling Input C External Clock XTI MCKPD = "0" 25k PMXTL = "1" XTO AK4538 Figure 15. External Clock mode (Input : 50%DVDD) - Note: This clock level must not exceed DVDD level. (C : 0.1F) MS0198-E-01 - 19 - 2003/5 ASAHI KASEI [AK4538] n System Clock (1) PLL Mode (PMPLL bit = "1") A fully integrated analog phase locked loop (PLL) generates a clock that is selected by the PLL1-0 and FS2-0 bits (see Table 2 and Table 3). The frequency of the MCKO output is selectable via the PS1-0 bits registers as defined in Table 4 and the MCKO output enable is controlled by the MCKO bit. If PS1-0 bits are changed before LRCK is input, MCKO is not output. PS1-0 bits should be changed after LRCK is input in slave mode. The PLL should be powered-up after the X'tal oscillator becomes stable or external master clock is inputted. If X'tal and PLL are powered-up at the same time or PLL is powered-up before external master clock is inputted, the PLL does not start. It takes X'tal oscillator 20ms(typ) to be stable after PMXTL bit= "1". The PLL needs 40ms lock time, whenever the sampling frequency changes or the PLL is powered-up (PMPLL bit= "0" "1"). If the sampling frequency is changed and the PLL goes to unlock state when the DAC is operated(PMDAC bit= "1"), the DAC data should be soft-muted or "0". In case of the ADC(PMADC bit = "1"), the ADC data acquired during the frequency change may be erroneous and therefore should not be used. LRCK and BICK are output from the AK4538 in master mode. When the clock input to MCKI pin stops during normal operation (PMPLL bit = "1"), the internal PLL continues to oscillate (a few MHz), and LRCK and BICK outputs go to "L" (see Table 5). In slave mode, the LRCK input should be synchronized with MCKO. The master clock (MCKI) should be synchronized with sampling clock (LRCK). The phase between these clocks does not matter. LRCK and BICK must be present whenever the AK4538 is operating (PMADC bit = "1" or PMDAC bit = "1"). If these clocks are not provided, the AK4538 may draw excess current due to its use of internal dynamically refreshed logic. If the external clocks are not present, place the AK4538 in power-down mode (PMADC bit = PMDAC bit = "0"). Mode 0 1 2 3 PLL1 PLL0 MCKI 0 0 12.288MHz 0 1 11.2896MHz 1 0 12MHz 1 1 N/A Table 2. MCKI Input Frequency (PLL Mode) FS1 FS0 Default FS2 0 0 0 0 1 1 1 1 Sampling Frequency Default 0 0 44.1kHz 0 1 22.05kHz 1 0 11.025kHz 1 1 48kHz 0 0 32kHz 0 1 24kHz 1 0 16kHz 1 1 8kHz Table 3. Sampling Frequency (PLL Mode) Mode PS1 PS0 MCKO 0 0 0 256fs Default 1 0 1 128fs 2 1 0 64fs 3 1 1 32fs Table 4. MCKO Frequency (PLL Mode, MCKO bit = "1") MS0198-E-01 - 20 - 2003/5 ASAHI KASEI [AK4538] MCKI pin MCKO pin BICK pin LRCK pin Master Mode (M/S pin = "H") Power up Power down PLL Unlock Frequency set by PLL1-0 Frequency set by PLL1-0 bits Refer to Table 1 bits (Refer to Table 2) (Refer to Table 2) MCKO bit = "0" : "L" MCKO bit = "0" : "L" "L" MCKO bit = "1" : Output MCKO bit = "1" : Unsettling BF bit = "0" : 64fs Output "L" "L" BF bit = "1" : 32fs Output Output "L" "L" Table 5. Clock Operation at Master Mode (PLL Mode) MCKI pin MCKO pin BICK pin LRCK pin Slave Mode (M/S pin = "L") Power up Power down PLL Unlock Frequency set by PLL1-0 Frequency set by PLL1-0 bits Refer to Table 1 bits (Refer to Table 2) (Refer to Table 2) MCKO bit = "0" : "L" MCKO bit = "0" : "L" "L" MCKO bit = "1" : Output MCKO bit = "1" : Unsettling Input Fixed to "L" or "H" externally Input Input Fixed to "L" or "H" externally Input Table 6. Clock Operation at Slave Mode (PLL Mode) (2) External mode (PMPLL bit = "0") When the PMPLL bit = "0", the AK4538 works in external clock mode. The MCKO pin outputs a buffered clock of MCKI input. For example, when MCKI = 256fs, the sampling frequency is changeable from 7kHz to 48kHz (Table 7). The MCKO bit controls MCKO output enable. The frequency of MCKO is selectable via register the PS1-0 bits as defined in Table 8. If PS1-0 bits are changed before LRCK is input, MCKO is not output. PS1-0 bits should be changed after LRCK is input in slave mode. The master clock frequency should be changed only when both the PMADC and PMDAC bits = "0". LRCK and BICK are output from the AK4538 in master mode. The clock to the MCKI pin must not stop during normal operation (PMPLL bit = "1"). If this clock is not provided, the AK4538 may draw excess current due to its use of internal dynamically refreshed logic. If the external clocks are not present, place the AK4538 in power-down mode (PMADC bit = PMDAC bit = "0"). MCKI, BICK and LRCK clocks are required in slave mode. The master clock (MCKI) should be synchronized with sampling clock (LRCK). The phase between these clocks does not matter. LRCK and BICK should always be present whenever the AK4538 is in normal operation (PMADC bit = "1" or PMDAC bit = "1"). If these clocks are not provided, the AK4538 may draw excess current due to its use of internal dynamically refreshed logic. If the external clocks are not present, place the AK4538 in power-down mode (PMADC bit = PMDAC bit = "0"). Mode 0 1 2 3 FS1 0 0 1 1 FS0 Sampling Frequency (fs) 0 7kHz 48kHz 1 7kHz 24kHz 0 7kHz 12kHz 1 7kHz 48kHz Table 7. Sampling Frequency Select (EXT Mode) MCKI 256fs 512fs 1024fs 256fs Default MS0198-E-01 - 21 - 2003/5 ASAHI KASEI [AK4538] Mode PS1 PS0 MCKO 0 0 0 256fs Default 1 0 1 128fs 2 1 0 64fs 3 1 1 32fs Table 8. MCKO Frequency (EXT Mode, MCKO bit = "1") Master Mode (M/S pin = "H") Power up Power down MCKO bit = "0" : "L" MCKO pin "L" MCKO bit = "1" : Output BF bit = "0" : 64fs Output BICK pin "L" BF bit = "1" : 32fs Output LRCK pin Output "L" Table 9. Clock Operation at Master Mode (EXT Mode) Slave Mode (M/S pin = "L") Power up Power down MCKO bit = "0" : "L" MCKO pin "L" MCKO bit = "1" : Output BICK pin Input Fixed to "L" or "H" externally LRCK pin Input Fixed to "L" or "H" externally Table 10. Clock Operation at Slave Mode (EXT Mode) The S/N of the DAC at low sampling frequencies is worse than at high sampling frequencies due to out-of-band noise. When the out-of-band noise can be improved by using higher frequency of the master clock. The S/N of the DAC output through Headphone amp at fs=8kHz is shown in Table 11. MCLK S/N (fs=8kHz, A-weighted) 256fs 84dB 512fs 88dB 1024fs 88dB Table 11. Relationship between MCLK and S/N of HP-AMP n Master Mode/Slave Mode The M/S pin selects either master or slave modes. M/S pin = "H" selects master mode and "L" selects slave mode. The AK4538 outputs MCKO, BICK and LRCK in master mode. The AK4538 outputs only MCKO in slave mode, while BICK and LRCK must be input separately. BICK / LRCK BICK = Input Slave Mode MCKO = Output LRCK = Input BICK = Output Master Mode MCKO = Output LRCK = Output Table 12. Master mode/Slave mode MCKO MS0198-E-01 - 22 - 2003/5 ASAHI KASEI [AK4538] n System Reset Upon power-up, reset the AK4538 by bringing the PDN pin = "L". This ensures that all internal registers reset to their initial values. The ADC enters an initialization cycle that starts when the PMADC bit is changed from "0" to "1". The initialization cycle time is 2081/fs, or 47.2ms@fs=44.1kHz. During the initialization cycle, the ADC digital data outputs of both channels are forced to a 2's compliment, "0". The ADC output reflects the analog input signal after the initialization cycle is complete. The DAC does not require an initialization cycle. n Audio Interface Format Three types of data formats are available and are selected by setting the DIF1-0 bits. In all modes, the serial data is MSB first, 2's complement format. The SDTO is clocked out on the falling edge of BICK and the SDTI is latched on the rising edge. All data formats can be used in both master and slave modes. LRCK and BICK are output from AK4538 in master mode, but must be input to AK4538 in slave mode. If 16-bit data that ADC outputs is converted to 8-bit data by removing LSB 8-bit, -1 at 16bit data is converted to -1 at 8-bit data. And when the DAC playbacks this 8-bit data, -1 at 8-bit data will be converted to -256 at 16-bit data and this is a large offset. This offset can be removed by adding the offset of 128 to 16-bit data before converting to 8-bit data. Mode 0 1 2 3 DIF1 0 0 1 1 DIF0 0 1 0 1 SDTO (ADC) SDTI (DAC) MSB justified LSB justified MSB justified MSB justified I2 S I2 S N/A N/A Table 13. Audio Interface Format BICK 32fs 32fs 32fs N/A Figure Figure 16 Figure 17 Figure 18 - Default LRCK 0123 9 10 11 12 13 14 15 0 1 2 3 9 10 11 12 13 14 15 0 1 BICK(32fs) SDTO(o) SDTI(i) BICK(64fs) SDTO(o) SDTI(i) 15 14 13 Don't Care 15:MSB, 0:LSB Lch Data Rch Data 10 15 14 10 Don't Care 15 14 210 15 15 14 13 15 14 13 0123 76543210 7 6 5 4 3 2 1 0 15 14 13 15 16 17 18 31 0 1 2 3 15 7 6 5 4 3 2 1 0 15 15 16 17 18 31 0 1 Figure 16. Mode 0 Timing MS0198-E-01 - 23 - 2003/5 ASAHI KASEI [AK4538] LRCK 0123 9 10 11 12 13 14 15 0 1 2 3 9 10 11 12 13 14 15 0 1 BICK(32fs) SDTO(o) SDTI(i) BICK(64fs) SDTO(o) SDTI(i) 15 14 13 15 14 13 15:MSB, 0:LSB Lch Data Rch Data 10 10 Don't Care 15 14 13 10 Don't Care 15 15 15 14 13 15 14 13 0123 76543210 7 6 5 4 3 2 1 0 15 14 13 15 16 17 18 31 0 1 2 3 15 7 6 5 4 3 2 1 0 15 15 16 17 18 31 0 1 Figure 17. Mode 1 Timing LRCK 0123 9 10 11 12 13 14 15 0 1 2 3 9 10 11 12 13 14 15 0 1 BICK(32fs) SDTO(o) SDTI(i) BICK(64fs) SDTO(o) SDTI(i) 15 14 15 14 210 210 Don't Care 15 14 210 Don't Care 15 14 0 15 14 0123 876543210 8 7 6 5 4 3 2 1 0 15 14 15 16 17 18 31 0 1 2 3 876543210 15 16 17 18 31 0 1 15:MSB, 0:LSB Lch Data Rch Data Figure 18. Mode 2 Timing n Digital High Pass Filter The ADC has a digital high pass filter for DC offset cancellation. The cut-off frequency of the HPF is 3.4Hz (@fs=44.1kHz) and scales with sampling rate (fs). MS0198-E-01 - 24 - 2003/5 ASAHI KASEI [AK4538] n MIC Input "ATTM" ATT "MICL" Stereo Mixer "MICM" Mono Mixer P "ATTS2-0" "MGAIN" Mic In 0dB/+20dB IPGA with ALC "ALC1" "IPGA6-0" ATT ADC "MICAD" Figure 19. Microphone Input The AK4538 has the following functions for Mic Input. (1) 1st MIC Amplifier of 20dB gain that can be selected on/off by "MGAIN" bit. (2) 2nd Amplifier that has PGA with ALC. This volume is controlled by "IPGA6-0" bit as Table 14. While ALC is working, Master Clock must be present. When Master Clock isn't provided or PMMIC= "0", it is invalid to write to "IPGA6-0". (3) Attenuator for stereo mixer. This volume is controlled by "ATTS2-0" bit as Table 15. (4) Attenuator for mono mixer. This attenuator level is 4dB and this ON/OFF is controlled by "ATTM" bit. IPGA6-0 GAIN (dB) STEP 47H +27.5 46H +27.0 45H +26.5 : : 36H +19.0 : : 10H +0.0 Default : : 0.5dB 06H -5.0 05H -5.5 04H -6.0 03H -6.5 02H -7.0 01H -7.5 00H -8.0 Table 14. Microphone Input Gain Setting ATTS2-0 Attenuation 7H -6dB 6H -9dB Default 5H -12dB 4H -15dB 3H -18dB 2H -21dB 1H -24dB 0H -27dB Table 15. Attenuator Table MS0198-E-01 - 25 - 2003/5 ASAHI KASEI [AK4538] n MIC Gain Amplifier AK4538 has a Gain Amplifier for Microphone input. This gain is 0dB or +20dB, selected by the MGAIN bit. The typical input impedance is 30k. MGAIN bit Input Gain 0 0dB 1 +20dB Table 16. Input Gain Default n MIC Power The MPI and MPE pins supply power for the Microphone. These output voltages are 0.75 x AVDD (typ) and the maximum output current is 1.25mA. MPWRI/MPWRE bit can control output from MPI and MPE pin. "MPWRE" bit MPE MPI INT EXT "MPWRI" bit MDT "DTMIC" bit 500k 0.075 x AVDD Figure 20. Microphone Power Supply n MIC Detection Function The AK4538 includes the detection function of microphone. Example of the detection of external microphone. (1) MPWRE= "1". (2) MPE drives external microphone. (3) DTMIC bit is set by Table 17. Input Level of DTM DTMIC External microphone 1 Connect 0.075 x AVDD < 0.050 x AVDD 0 Disconnect Table 17. Microphone detection result MS0198-E-01 - 26 - 2003/5 ASAHI KASEI [AK4538] n Manual Mode The AK4538 becomes a manual mode at ALC1 bit = "0". This mode is used in the case shown below. 1. After exiting reset state, set up the registers for the ALC1 operation (ZTM1-0, LMTH and etc) 2. When the registers for the ALC1 operation (Limiter period, Recovery period and etc) are changed. For example; When the change of the sampling frequency. 3. When IPGA is used as a manual volume. When writing to the IPGA6-0 bits continually, the control register should be written by an interval more than zero crossing timeout. n MIC-ALC Operation The ALC (Automatic Level Control) of MIC input is done by ALC1 block when ALC1 bit is "1". [1] ALC1 Limiter Operation When the ALC1 limiter is enabled, and IPGA output exceeds the ALC1 limiter detection level (LMTH), the IPGA value is attenuated by the amount defined in the ALC1 limiter ATT step (LMAT1-0 bits) automatically. When the ZELM bit = "1", the timeout period is set by the LTM1-0 bits. The operation for attenuation is done continuously until the input signal level becomes LMTH or less. If the ALC1 bit does not change into "0" after completing the attenuation, the attenuation operation repeats while the input signal level equals or exceeds LMTH. When the ZELM bit = "0", the timeout period is set by the ZTM1-0 bits. This enables the zero-crossing attenuation function so that the IPGA value is attenuated at the zero-detect points of the waveform. [2] ALC1 Recovery Operation The ALC1 recovery refers to the amount of time that the AK4538 will allow a signal to exceed a predetermined limiting value prior to enabling the limiting function. The ALC1 recovery operation uses the WTM1-0 bits to define the wait period used after completing an ALC1 limiter operation. If the input signal does not exceed the "ALC1 Recovery Waiting Counter Reset Level", the ALC1 recovery operation starts. The IPGA value increases automatically during this operation up to the reference level (REF6-0 bits). The ALC1 recovery operation is done at a period set by the WTM1-0 bits. Zero crossing is detected during WTM1-0 period, the ALC1 recovery operation waits WTM1-0 period and the next recovery operation starts. During the ALC1 recovery operation, when input signal level exceeds the ALC1 limiter detection level (LMTH), the ALC1 recovery operation changes immediately into an ALC1 limiter operation. In the case of "(Recovery waiting counter reset level) IPGA Output Level < Limiter detection level" during the ALC1 recovery operation, the wait timer for the ALC1 recovery operation is reset. Therefore, in the case of "(Recovery waiting counter reset level) > IPGA Output Level", the wait timer for the ALC1 recovery operation starts. The ALC1 operation corresponds to the impulse noise. When the impulse noise is input, the ALC1 recovery operation becomes faster than a normal recovery operation. MS0198-E-01 - 27 - 2003/5 ASAHI KASEI [AK4538] [3] Example of ALC1 Operation Table 15 shows the examples of the ALC1 setting. In case of this examples, ALC1 operation starts from 0dB. Register Name LMTH LTM1-0 ZELM ZTM1-0 WTM1-0 REF6-0 IPGA6-0 LMAT1-0 RATT ALC1 Comment fs=8kHz Data Operation 1 -4dBFS 00 Don't use 0 Enable 00 16ms fs=16kHz Data Operation 1 -4dBFS 00 Don't use 0 Enable 01 16ms 16ms +27.5dB 0dB 1 step 1 step Enable fs=44.1kHz Data Operation 1 -4dBFS 00 Don't use 0 Enable 10 11.6ms 10 47H 10H 00 0 1 11.6ms +27.5dB 0dB 1 step 1 step Enable Limiter detection Level Limiter operation period at ZELM = 1 Limiter zero crossing detection Zero crossing timeout period Recovery waiting period *WTM1-0 bits should be the same data 00 16ms 01 as ZTM1-0 bits Maximum gain at recovery operation 47H +27.5dB 47H Gain of IPGA at ALC1 operation start 10H 0dB 10H Limiter ATT Step 00 1 step 00 Recovery GAIN Step 0 1 step 0 ALC1 Enable bit 1 Enable 1 Table 18. Example of the ALC1 setting The following registers should not be changed during the ALC1 operation. These bits should be changed, after the ALC1 operation is finished by ALC1 bit = "0" or PMMIC bit = "0". * LTM1-0, LMTH, LMAT1-0, WTM1-0, ZTM1-0, RATT, REF6-0, ZELM bits IPGA gain at ALC1 operation start can be changed from the default value of IPGA6-0 bits while PMMIC bit is "1" and ALC1 bit is "0". When ALC1 bit is changed from "1" to "0", IPGA holds the last gain value set by ALC1 operation. Example: Limiter = Zero crossing Enable Recovery Cycle = 16ms @ fs= 8kHz Limiter and Recovery Step = 1 Maximum Gain = +27.5dB Limiter Detection Level = -4dBFS Manual Mode ALC2 bit = "1" (default) (1) Addr=08H, Data=00H WR (ZTM1-0, WTM1-0, LTM1-0) WR (REF6-0) (2) Addr=0AH, Data=47H WR (IPGA6-0) * The value of IPGA should be the same or smaller than REF's (3) Addr=0BH, Data=10H WR (ALC1= "1", LMAT1-0, RATT, LMTH, ZELM) (4) Addr=09H, Data=61H ALC1 Operation Note : WR : Write Figure 21. Registers set-up sequence at ALC1 operation MS0198-E-01 - 28 - 2003/5 ASAHI KASEI [AK4538] n De-emphasis Filter The AK4538 includes the digital de-emphasis filter (tc = 50/15s) by IIR filter. Setting the DEM1-0 bits enables the de-emphasis filter. DEM1 0 0 1 1 DEM0 Mode 0 44.1kHz 1 OFF Default 0 48kHz 1 32kHz Table 19. De-emphasis Control n Bass Boost Function The BST1-0 bits control the amount of low frequency boost applied to the DAC output signal. If the BST1-0 bits are set to "10" (MID Level), use a 47F capacitor for AC-coupling. If the boosted signal exceeds full scale, the analog output clips to the full scale. Figure 22 shows the boost frequency response at -20dB signal input. Boost Frequency (fs=44.1kHz) 0 Output Level [dB] -5 -10 -15 -20 -25 0.01 0.1 Frequency [kHz] Figure 22. Boost Frequency (fs=44.1kHz) BST1 BST0 Mode 0 0 OFF Default 0 1 MIN 1 0 MID 1 1 MAX Table 20. Low Frequency Boost Control MIN MAX MID 1 10 MS0198-E-01 - 29 - 2003/5 ASAHI KASEI [AK4538] n Digital Attenuator The AK4538 has a channel-independent digital attenuator (256 levels, 0.5dB step, Mute). The attenuation level of each channel can be set by the ATTL/R7-0 bits (Table 21). When the DATTC bit = "1", the ATTL7-0 bits control both Lch and Rch attenuation levels. When the DATTC bit = "0", the ATTL7-0 bits control Lch level and ATTR7-0 bits control Rch level. This attenuator has a soft transition function. It takes 1061/fs from 00H to FFH. ATTL/R7-0 Attenuation 00H 0dB Default 01H -0.5dB 02H -1.0dB 03H -1.5dB : : : : FDH -126.5dB FEH -127.0dB FFH MUTE (-) Table 21. DATT Code Table n Soft Mute Soft mute operation is performed in the digital domain. When the SMUTE bit goes to a "1", the output signal is attenuated by - ("0") during the cycle set by the TM1-0 bits. When the SMUTE bit is returned to "0", the mute is cancelled and the output attenuation gradually changes to 0dB during the cycle set of the TM1-0 bits. If the soft mute is cancelled within the cycle set by the TM1-0 bits after starting the operation, the attenuation is discontinued and returned to 0dB. The soft mute is effective for changing the signal source without stopping the signal transmission. The soft mute function is independent of output volume and cascade connected between both functions. SMUTE bit T M 1-0 bit T M 1-0 bit 0dB Attenuation (1) (3) - GD (2) Analog Output GD Figure 23. Soft Mute Function NOTE: (1) The output signal is attenuated until - ("0") by the cycle set by the TM1-0 bits. (2) Analog output corresponding to digital input has the group delay (GD). (3) If the soft mute is cancelled within the cycle of setting the TM1-0 bits, the attenuation is discounted and returned to 0dB(the set value). MS0198-E-01 - 30 - 2003/5 ASAHI KASEI [AK4538] n AUX Input "GN3-0" AUXIN+ AUXIN- "AUXL" Stereo Mixer Volume "AUXAD" Mixer for ADC Figure 24. AUX Input AUX input is differential input. The AK4538 has a volume for AUX Input. This Volume is controlled by GN3-0 bits as shown in Table 22.The AK4538 register control for GN3-0 does not offer any de-clicking function at volume setting change. GN3-0 GAIN (dB) FH +24.0 EH +21.0 DH +18.0 : : 7H +0.0 Default : : 2H -15.0 1H -18.0 0H -21.0 Table 22. AUX Input Gain Setting MS0198-E-01 - 31 - 2003/5 ASAHI KASEI [AK4538] n BEEP Input When the BMBPS bit is set to "1", the stereo beep input is powered up. And when the BPSHP bit is set to "1", the input signals from the BEEPL and BEEPR pins are mixed to Headphone outputs. When the BPSSP bit is set to "1", the signal of (BEEPL + BEEPR)/2 is input to Speaker-amp. When the BMBPM bit is set to "1", mono beep input is powered up. And when the BPMHP bit is set to "1", the input signal from the BEEPM pin to Headphone-amp. When the BPMSP bit is set to "1", the signal from the BEEPM pin is input to Speaker output. The external resisters Ri adjust the signal level of each BEEP input that are mixed to Headphone and Speaker outputs. The signal from the BEEPM pin is mixed to the Headphone-amp through a -20dB gain stage. The signal from the BEEPM pin is mixed to the Speaker-amp without gain. The internal feedback resistance is 20k 30%. Rf = 20k Ri BEEPL BPMHP Rf = 20k Ri BEEPR BPSHP BPSSP Rf = 20k Ri BEEPM BPMSP 1/2 1/2 SPK MIX -20dB HPR MIX BPSHP HPL MIX AK4538 Figure 25. Block Diagram of BEEP pins MS0198-E-01 - 32 - 2003/5 ASAHI KASEI [AK4538] n Headphone Output Power supply voltage for the Headphone-amp is supplied from the HVDD pin and centered on the HVDD/2 voltage. The Headphone output load resistance is min.20. When the HPL and HPR bits are "1", output signals are muted and the HPL and HPR pins output HVDD/2 voltage. When the HPL and HPR bits are "0", the Headphone-amps are in normal operation. When the PMHPL and PMHPR bits are "0", the Headphone-amp is powered down and the outputs (HPL and HPR pins) go to "L" (HVSS). A capacitor between the MUTET pin and ground reduces pop noise at power-up. [Example] : A capacitor between the MUTET pin and ground = 1.0F, a capacitor between the HPL (HPR) pin and Headphone = 47F Time constant of rise time: r = 100ms, Time constant of fall time: f = 188ms PMHPL/R bits HPL/R pins (1) r (2) f Figure 26. Power-up/Power-down Timing for Headphone-amp Note: The HPL and HPR bits should be kept to "0" during power-up. (1) PMHPL and PMHPR bits = "1" Headphone-amp is powered up. Common voltage of Headphone-amp is rising. This rise time depends on the capacitor value connected with the MUTET pin. The time constant is r = 100k x C when the capacitor value on MUTET pin is "C". (2) PMHPL and PMHPR bits = "0" Headphone-amp is powered down. Common voltage is falling. This fall time depends on the internal resistor and the capacitor value of HPL/R pins. The time constant is f = 2k x (2 x C) when the capacitor value on HPL(HPR) pin is "C". If the power supply is powered off or Headphone-Amp is powered-up again before the common voltage goes to GND, some POP noise occurs. It takes 5times of f that the common voltage goes to GND. The cut-off frequency of Headphone-amp output depends on the external resistor and capacitor used. Table 18 shows the cut off frequency and the output power for various resistor/capacitor combinations. The headphone impedance RL is 16. Output powers are shown at HVDD = 2.7, 3.0 and 3.3V. The output voltage of headphone is 0.6 x AVDD (Vpp). When an external resistor R is smaller than 12, put an oscillation prevention circuit (0.22F+10) because it has the possibility that Headphone-amp oscillates. HP-AMP R C Headphone 16 AK4538 0.22 10 Figure 27. External Circuit Example of Headphone R [] 6.2 16 6.2 16 C [F] 47 47 100 100 fc [Hz] fc [Hz] Output Power [mW] BOOST=OFF BOOST=MID 2.7V 3.0V 152.5 63 10.0 12.4 105.8 43 4.8 6.0 71.2 27 10.0 12.4 49.7 20 4.8 6.0 Table 23. External Circuit Example 3.3V 15.0 7.2 15.0 7.2 MS0198-E-01 - 33 - 2003/5 ASAHI KASEI [AK4538] n Speaker Output Mono signal [(L+R)/2] converted from stereo DAC output and BEEP input signal can be output via Speaker-amp which is controlled by BTL. ALC2 circuit is available for DAC output signal. This Speaker-amp can deliver a maximum power of 300mW(typ)@THD=10%, 250mW(typ)@THD=0.1% into 8 ohm load at HVDD=3.3V. Maximum output power is 137mW(typ) when DAC output signal is output via ALC2 circuit as system design example (Figure 46). When BEEP input is used for DAC output, maximum power becomes 300mW. Figure 29 and Figure 30 indicates connection examples for 300mW output. Speaker blocks (MOUT2, ALC2 and Speaker-amp) can be powered up/down by controlling the PMSPK bit. When the PMSPK bit is "0", the MOUT2, SPP and SPN pins are placed in a Hi-Z state. When the SPPS bit is "0", the Speaker-amp enters power-save-mode. In this mode, the SPP pin is placed in a Hi-Z state and the SPN pin goes to HVDD/2 voltage. And then the Speaker output gradually changes to the HVDD/2 voltage and this mode can reduce pop noise at power-up. When the AK4538 is powered down, pop noise can be also reduced by first entering power-save-mode. PMSPK bit SPPS bit SPP pin Hi-Z Hi-Z SPN pin Hi-Z HVDD/2 HVDD/2 Hi-Z Figure 28. Power-up/Power-down Timing for Speaker-amp [Connection Example for 300mW output] (1) Using BEEPM pin AK4538 20k 30% SPK-Amp SPP BPMSP SPN MOUT2 0.047u 45%AVDD BEEPM 13k Figure 29. Connection example for 300mW output using BEEPM pin MS0198-E-01 - 34 - 2003/5 ASAHI KASEI [AK4538] (2) Using BEEPL and BEEPR pins AK4538 20k 30% BPSSP SPK-Amp 45%AVDD 20k 30% SPN SPP BPSSP 45%AVDD MOUT2 0.1u BEEPL 15k BEEPR 15k Figure 30. Connection example for 300mW output using BEEPL and BEEPR pins Note) 1. MOUT2 output is recommended to be AC coupled to avoid amplified DC offset of common voltage of MOUT2 and BEEP-Amp is output via BTL Speaker-Amp (that means stand-by current is increased). Capacitor size affects the cut-off frequency of 1st order LPF made by this AC coupling capacitor and series resister in front of BEEP input. 2. BEEP input path has 1.9dB greater gain than MIN input since ALC2 circuit is not included in BEEP path. 3. Internal feedback resister of BEEP-Amp which determines BEEP-Amp gain has 30% sample variation. n MONO OUTPUT (MOUT2 pin) The mixed Lch/Rch signal of DAC is output from the MOUT2 pin. When the MOUT2 bit is "0", this output is OFF and the MOUT2 pin is forced to VCOM voltage. The load impedance is 10k (min.). When the PMSPK bit is "0", the Speaker-amp enters power-down-mode and the output is placed in a Hi-Z state. MS0198-E-01 - 35 - 2003/5 ASAHI KASEI [AK4538] n ALC2 Operation Input resistance of the ALC2 is 24k (typ) and centered around VCOM voltage, and the input signal level is -3.1dBV. (see Figure 31. 0dBV=1Vrms=2.828Vpp) The limiter detection level is proportional to HVDD. The output level is limited by the ALC2 circuit when the input signal exceeds -5.2dBV (=FS-1.9dB@HVDD=3.3V). When a continuous signal of -5.2dBV or greater is input to the ALC2 circuit, the change period of the ALC2 limiter operation is set by the ROTM bit and the attenuation level is 0.5dB/step. The ALC2 recovery operation uses zero crossings and gains of 1dB/step. The ALC2 recovery operation is done until the input level of the Speaker-amp goes to -7.2dBV(=FS-3.9dB@HVDD=3.3V). The ROTM bit sets the ALC2 recovery operation period. When the input signal is between -5.2dBV and -7.2dBV, the ALC2 limiter or recovery operations are not done. When the PMSPK bit changes from "0" to "1", the initilization cycle (2048/fs = 46.4ms @fs=44.1kHz at ROTM bit = "0", 512/fs = 11.4ms @fs=44.1kHz at the ROTM bit = "1") starts. The ALC2 is disabled during the initilization cycle and the ALC2 starts after completing the initilization cycle. Parameter ALC2 Limiter operation ALC2 Recovery operation Operation Start Level -5.2dBV -7.2dBV ROTM bit = "0" 2048/fs=46.4ms (at 44.1kHz) 2/fs = 45s (at 44.1kHz) Period ROTM bit = "1" 512/fs=46.4ms (at 11.025kHz) 2/fs = 180s (at 11.025kHz) Zero-crossing Detection No Yes (Timeout = Period Time) ATT/GAIN 0.5dB step 1dB step Table 24. Limiter /Recovery of ALC2 at HVDD=3.3V Full-differential FS-1.9dB = -5.2dBV 0.4dBV 0dBV -3.3dBV -3.3dBV FS -8dB -11.3dBV -1.9dB +4.1dB +5.6dB -1.6dBV -5.6dBV Single-ended -10dBV -0.4dB +8.1dB FS-3.9dB = -7.2dBV +16.1dB -15.3dBV -15.3dBV FS-12dB -8dB -23.3dBV -20dBV -30dBV ATT+DAC ALC2 SPK-AMP Figure 31. Speaker-amp Output Level Diagram (HVDD=3.3V, DATT=-8.0dB) MS0198-E-01 - 36 - 2003/5 ASAHI KASEI [AK4538] n Stereo LINE OUTPUT (LOUT and ROUT pins) MIC In 0dB/+20dB IPGA "MICL" "DAHS" ATT+DAC ATT Stereo Line Out AUXIN+ AUXIN"AUXL" Volume Figure 32. Stereo Line Output Line out path doesn't have Volume but the output signal level can be controlled by the attenuator of DAC, Volume of Mic In and AUX In. There aren't mute circuits to remove POP noise at power up and down for Line Output. n MONO LINE OUTPUT (MOUT+ and MOUT- pins) MIC In 0dB/+20dB IPGA "MICM" "DAMO" "MOGN" 1/2 ATT+DAC MOUT+ MOUT-17dB/6dB 1/2 Figure 33. Mono Output Mono mixer mixes signal from MIC In, Lch signal and Rch signal from DAC. This mixed signal is output from the MOUT+ and MOUT- pins, creating a differential output. Either the MOUT+ or MOUT- pins can be also used as single-ended output. Amp for mono output has 6dB gain and -17dB gain that are set by the MOGN bit. MS0198-E-01 - 37 - 2003/5 ASAHI KASEI [AK4538] n Serial Control Interface (1) 4-wire Serial Control Mode (I2C pin = "L") Internal registers may be written by using the 4-wire P interface pins (CSN, CCLK, CDTI and CDTO). The data on this interface consists of a 2-bit Chip address, Read/Write, Register address (MSB first, 5bits) and Control data (MSB first, 8bits). The chip address high bit is fixed to "1" and the lower bit is set by the CAD0 pin. Address and data is clocked in on the rising edge of CCLK and data is clocked out on the falling edge. After a low-to-high transition of CSN, data is latched for write operations and CDTO bit outputs Hi-Z. The clock speed of CCLK is 5MHz (max). The value of internal registers is initialized at PDN pin = "L". CSN 0 CCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CDTI Write CDTO C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 Hi-Z CDTI Read CDTO C1 C0 R/W A4 A3 A2 A1 A0 Hi-Z C1 - C0 : Chip Address (C1="1", C0=CAD0) R/W : READ / WRITE ("1" : WRITE, "0" : READ) A4 - A0 : Register Address D7 - D0 : Control Data D7 D6 D5 D4 D3 D2 D1 D0 Hi-Z Figure 34. Serial Control I/F Timing MS0198-E-01 - 38 - 2003/5 ASAHI KASEI [AK4538] (2) I2C-bus Control Mode (I2C pin = "H") The AK4538 supports the standard-mode I2C-bus (max: 100kHz). The AK4538 does not support a fast-mode I2C-bus system (max: 400kHz). (2)-1. WRITE Operations Figure 35 shows the data transfer sequence for the I2C-bus mode. All commands are preceded by a START condition. A HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START condition (Figure 41). After the START condition, a slave address is sent. This address is 7 bits long followed by an eighth bit that is a data direction bit (R/W). The most significant five bits of the slave address are fixed as "00100". The next two bits are CAD1 and CAD0 (device address bits). These two bits identify the specific device on the bus. The hard-wired input pins (CAD1 and CAD0 pins) set these device address bits (Figure 36). If the slave address matches that of the AK4538, the AK4538 generates an acknowledge and the operation is executed. The master must generate the acknowledge-related clock pulse and release the SDA line (HIGH) during the acknowledge clock pulse (Figure 42). A R/W bit value of "1" indicates that the read operation is to be executed. A "0" indicates that the write operation is to be executed. The second byte consists of the control register address of the AK4538. The format is MSB first, and those most significant 3-bits are fixed to zeros (Figure 37). The data after the second byte contains control data. The format is MSB first, 8bits (Figure 38). The AK4538 generates an acknowledge after each byte has been received. A data transfer is always terminated by a STOP condition generated by the master. A LOW to HIGH transition on the SDA line while SCL is HIGH defines a STOP condition (Figure 41). The AK4538 can perform more than one byte write operation per sequence. After receipt of the third byte the AK4538 generates an acknowledge and awaits the next data. The master can transmit more than one byte instead of terminating the write cycle after the first data byte is transferred. After receiving each data packet the internal 5-bit address counter is incremented by one, and the next data is automatically taken into the next address. If the address exceeds 0FH prior to generating the stop condition, the address counter will "roll over" to 00H and the previous data will be overwritten. The data on the SDA line must remain stable during the HIGH period of the clock. The HIGH or LOW state of the data line can only change when the clock signal on the SCL line is LOW (Figure 43) except for the START and STOP conditions. S T A R T R/W="0" S T O P Sub Address(n) Data(n) A C K A C K Data(n+1) A C K A C K Data(n+x) A C K P SDA Slave S Address A C K Figure 35. Data Transfer Sequence at the I2C-Bus Mode 0 0 1 0 0 CAD1 CAD0 R/W (Those CAD1/0 should match with CAD1/0 pins) Figure 36. The First Byte 0 0 0 A4 A3 A2 A1 A0 Figure 37. The Second Byte D7 D6 D5 D4 D3 D2 D1 D0 Figure 38. Byte Structure after the second byte MS0198-E-01 - 39 - 2003/5 ASAHI KASEI [AK4538] (2)-2. READ Operations Set the R/W bit = "1" for the READ operation of the AK4538. After transmission of data, the master can read the next address's data by generating an acknowledge instead of terminating the write cycle after the receipt of the first data word. After receiving each data packet the internal 5-bit address counter is incremented by one, and the next data is automatically taken into the next address. If the address exceeds 0FH prior to generating a stop condition, the address counter will "roll over" to 00H and the previous data will be overwritten. The AK4538 supports two basic read operations: CURRENT ADDRESS READ and RANDOM ADDRESS READ. (2)-2-1. CURRENT ADDRESS READ The AK4538 contains an internal address counter that maintains the address of the last word accessed, incremented by one. Therefore, if the last access (either a read or write) were to address n, the next CURRENT READ operation would access data from the address n+1. After receipt of the slave address with R/W bit set to "1", the AK4538 generates an acknowledge, transmits 1-byte of data to the address set by the internal address counter and increments the internal address counter by 1. If the master does not generate an acknowledge to the data but instead generates a stop condition, the AK4538 ceases transmission. S T A R T S T O P Data(n) A C K A C K Data(n+1) A C K Data(n+2) A C K A C K Data(n+x) A C K P R/W="1" SDA Slave S Address Figure 39. CURRENT ADDRESS READ (2)-2-2. RANDOM ADDRESS READ The random read operation allows the master to access any memory location at random. Prior to issuing the slave address with the R/W bit set to "1", the master must first perform a "dummy" write operation. The master issues a start request, a slave address (R/W bit = "0") and then the register address to read. After the register address is acknowledged, the master immediately reissues the start request and the slave address with the R/W bit set to "1". The AK4538 then generates an acknowledge, 1 byte of data and increments the internal address counter by 1. If the master does not generate an acknowledge to the data but instead generates a stop condition, the AK4538 ceases transmission. S T A R T S T A R T Sub Address(n) A C K A C K R/W="0" R/W="1" S T O P Data(n) Data(n+1) A C K A C K A C K Data(n+x) A C K P SDA Slave S Address Slave S Address A C K Figure 40. RANDOM ADDRESS READ MS0198-E-01 - 40 - 2003/5 ASAHI KASEI [AK4538] SDA SCL S start condition P stop condition Figure 41. START and STOP Conditions DATA OUTPUT BY TRANSMITTER not acknowledge DATA OUTPUT BY RECEIVER acknowledge SCL FROM MASTER S clock pulse for acknowledgement 1 2 8 9 START CONDITION Figure 42. Acknowledge on the I2C-Bus SDA SCL data line stable; data valid change of data allowed Figure 43. Bit Transfer on the I2C-Bus MS0198-E-01 - 41 - 2003/5 ASAHI KASEI [AK4538] n Register Map Addr 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH Register Name Power Management 1 Power Management 2 Signal Select 1 Signal Select 2 Mode Control 1 Mode Control 2 DAC Control MIC Control Timer Select ALC Mode Control 1 ALC Mode Control 2 Input PGA Control Lch Digital ATT Control Rch Digital ATT Control Volume Control Status D7 PMVCM MCKPD MOGN DAHS PLL1 FS2 TM1 0 0 0 0 0 ATTL7 ATTR7 ATTM 0 D6 PMBPS PMXTL PSMO PSLO PLL0 FS1 TM0 0 ROTM ALC2 REF6 IPGA6 ATTL6 ATTR6 ATTS2 0 D5 PMBPM PMPLL DAMO AUXL PS1 FS0 SMUTE AUXAD ZTM1 ALC1 ERF5 IPGA5 ATTL5 ATTR5 ATTS1 0 D4 PMLO 0 MICM MICL PS0 HPRM DATTC MPWRE ZTM0 ZELM REF4 IPGA4 ATTL4 ATTR4 ATTS0 0 D3 PMMO PMSPK BPSSP BPSHP MCKO HPLM BST1 MPWRI WTM1 LMAT1 REF3 IPGA3 ATTL3 ATTR3 GN3 0 D2 PMAUX PMHPL BPMSP BPMHP BF HPM BST0 MICAD WTM0 LMAT0 REF2 IPGA2 ATTL2 ATTR2 GN2 0 D1 PMMIC PMHPR ALCS HPL DIF1 LOOP DEM1 MSEL LTM1 RATT REF1 IPGA1 ATTL1 ATTR1 GN1 0 D0 PMADC PMDAC MOUT2 HPR DIF0 SPPS DEM0 MGAIN LTM0 LMTH REF0 IPGA0 ATTL0 ATTR0 GN0 DTMIC The PDN pin = "L" resets the registers to their default values. Note: Unused bits must contain a "0" value. Note: Only write to address 00H to 0EH. MS0198-E-01 - 42 - 2003/5 ASAHI KASEI [AK4538] n Register Definitions Addr 00H Register Name Power Management 1 R/W Default D7 PMVCM R/W 0 D6 PMBPS R/W 0 D5 PMBPM R/W 0 D4 PMLO R/W 0 D3 PMMO R/W 0 D2 PMAUX R/W 0 D1 PMMIC R/W 0 D0 PMADC R/W 0 PMADC: ADC Block Power Control 0: Power down (Default) 1: Power up When the PMADC bit changes from "0" to "1", the initialization cycle (2081/fs=47.2ms@44.1kHz) starts. After initializing, digital data of the ADC is output. PMMIC: MIC In Block Power Control 0: Power down (Default) 1: Power up PMAUX: AUX In Power Control 0: Power down (Default) 1: Power up PMMO: Mono Line Out Power Control 0: Power down (Default) 1: Power up PMLO: Line Out Power Control 0: Power down (Default) 1: Power up PMBPM: Mono BEEP In Power Control 0: Power down (Default) 1: Power up Even if PMBPM= "0", the path is still connected between BEEPM and HP/SPK-Amp. BPMHP and BPMSP bits should be set to "0" to disconnect these paths, respectively. PMBPS: Stereo BEEP In Power Control 0: Power down (Default) 1: Power up Even if PMBPS= "0", the path is still connected between BEEPL/R and HP/SPK-Amp. BPSHP and BPSSP bits should be set to "0" to disconnect these paths, respectively. PMVCM: VCOM Block Power Control 0: Power down (Default) 1: Power up Each block can be powered down respectively by writing "0" in each bit. When the PDN pin is "L", all blocks are powered down. When all bits except MCKPD bit are "0" in the 00H and 01H addresses, all blocks are powered down. The register values remain unchanged. IPGA gain is reset when PMMIC bit is "0" (refer to the IPGA6-0 bits description). When any of the blocks are powered up, the PMVCM bit must be set to "1". MCLK, BICK and LRCK must always be present unless PMMIC=PMADC=PMDAC=PMSPK= "0" or PDN pin = "L". The paths from BEEP to HP-Amp and SPK-Amp can operate without these clocks. MS0198-E-01 - 43 - 2003/5 ASAHI KASEI [AK4538] Addr 01H Register Name Power Management 2 R/W Default D7 MCKPD R/W 1 D6 PMXTL R/W 0 D5 PMPLL R/W 0 D4 0 RD 0 D3 PMSPK R/W 0 D2 PMHPL R/W 0 D1 PMHPR R/W 0 D0 PMDAC R/W 0 PMDAC: DAC Block Power Control 0: Power down (Default) 1: Power up PMHPR: Rch of Headphone-Amp Power Control 0: Power down (Default) 1: Power up PMHPL: Lch of Headphone-Amp Power Control 0: Power down (Default) 1: Power up PMSPK: Speaker Block Power Control 0: Power down (Default) 1: Power up PMPLL: PLL Block Power Control Select 0: PLL is Power down and External is selected. (Default) 1: PLL is Power up and PLL Mode is selected. PMXTL: X'tal Oscillation Block Power Control 0: Power down (Default) 1: Power up MCKPD: MCKI pin pull down control 0: Master Clock input enable 1: Pulled down by 25k (Default) MS0198-E-01 - 44 - 2003/5 ASAHI KASEI [AK4538] Addr 02H Register Name Signal Select 1 R/W Default D7 MOGN R/W 0 D6 PSMO R/W 0 D5 DAMO R/W 0 D4 MICM R/W 0 D3 BPSSP R/W 0 D2 BPMSP R/W 0 D1 ALCS R/W 0 D0 MOUT2 R/W 0 MOUT2: MOUT2 Output Enable (Mixing = (L+R)/2) 0: OFF (Default) 1: ON When the MOUT2 bit = "0", the MOUT2 pin outputs VCOM voltage. The MOUT2 pin outputs signal at the MOUT2 bit = "1". This bit is valid at the PMSPK bit = "1". Hi-Z is output at the PMSPK bit = "0". ALCS: ALC2 to Speaker-amp Enable 0: OFF (Default) 1: ON ALC2 output signal is mixed to Speaker-amp at the ALCS bit = "1". BPMSP: BEEPM to Speaker-amp Enable 0: OFF (Default) 1: ON Mono BEEP signal (BEEPM pin) is mixed to Speaker-amp at the BPMSP bit = "1". BPSSP: BEEPL/BEEPR to Speaker-amp Enable 0: OFF (Default) 1: ON Stereo BEEP signals (BEEPL/BEEPR pins) are mixed to Speaker-amp at the BPSSP bit = "1". MICM: Switch Control from Mic In to Mono Mixer. 0: OFF (Default) 1: ON DAMO: DAC to MOUT+/MOUT- Enable 0: OFF (Default) 1: ON DAC output signal is output through Mono Line Output (MOUT+/MOUT-pins) at the DAMO bit = "1". PSMO: MOUT+/MOUT- Output Enable (Mixing = (L+R)/2) 0: Power Save Mode (Default) 1: ON When the PSMO bit = "0", Mono Line Output is in power save mode and the MOUT+ and MOUT- pins output 0.45 x AVDD voltage. MOGN: Gain control for mono output 0: +6dB (Default) 1: -17dB MS0198-E-01 - 45 - 2003/5 ASAHI KASEI [AK4538] ATT MIC In 0dB/+20dB IPGA "MICL" "DAHS" ATT+DAC "ALCS" ALC2 1/2 1/2 SPK-AMP AUXIN+ AUXINBEEPM BEEPL BEEPR "AUXL" Volume "BPMSP" "BPSSP" Figure 44. Speaker-amp switch control Addr 03H Register Name Signal Select 2 R/W Default D7 DAHS R/W 0 D6 PSLO R/W 0 D5 AUXL R/W 0 D4 MICL R/W 0 D3 BPSHP R/W 0 D2 BPMHP R/W 0 D1 HPL R/W 1 D0 HPR R/W 1 HPR: Rch Headphone-amp Disable 0: Normal Operation 1: OFF(Default) The HPR bit should be always "0" during operation. HPL: Lch Headphone-amp Disable 0: Normal Operation 1: OFF(Default) The HPL bit should be always "0" during operation. BPMHP: BEEPM to Headphone-amp Enable 0: OFF (Default) 1: ON Mono BEEP signal (BEEPM) is mixed to Headphone-amp at the BPMHP bit = "1". BPSHP: BEEPL/BEEPR to Headphone-amp Enable 0: OFF (Default) 1: ON Stereo BEEP signals (BEEPL/BEEPR) is mixed to Headphone-amp at the BPSHP bit = "1". MICL: Switch Control from MIC IN to Stereo Mixer. 0: OFF (Default) 1: ON AUXL: Switch Control from AUX IN to Stereo Mixer. 0: OFF (Default) 1: ON MS0198-E-01 - 46 - 2003/5 ASAHI KASEI [AK4538] PSLO: Select LINEOUT 0: Power Save Mode (Default) 1: ON When the PSLO bit = "0", Stereo Line Output is in power save mode and the LOUT+ and ROUT- pins output 0.45 x AVDD voltage. DAHS: DAC to Headphone-amp and MOUT2 Enable 0: OFF (Default) 1: ON DAC signal is mixed to Headphone-amp and MOUT2 at the DAHS bit = "1". "MICL" HPL ATT MIC IN 0dB/+20dB IPGA "DAHS" ATT+DAC HPL MUTE AUXIN+ AUXINBEEPM IN BEEPL IN BEEPR IN "AUXL" Volume "BPMHP" HPR HPR MUTE "BPSHP" Figure 45. Headphone-amp switch control MS0198-E-01 - 47 - 2003/5 ASAHI KASEI [AK4538] Addr 04H Register Name Mode Control 1 R/W Default D7 PLL1 R/W 0 D6 PLL0 R/W 0 D5 PS1 R/W 0 D4 PS0 R/W 0 D3 MCKO R/W 0 D2 BF R/W 0 D1 DIF1 R/W 1 D0 DIF0 R/W 0 DIF1-0: Audio Interface Format Select (see Table 13) Default: "10" (ADC: I2S, DAC: I2S) BF: BICK frequency Select at Master Mode 0: 64fs (Default) 1: 32fs This bit is invalid in slave mode. MCKO: Master Clock Output Enable 0: Disable (Default) 1: Enable PS1-0: Output Master Clock Select (see Table 4, 8) Default: "00" (256fs) PLL1-0: Input Master Clock Select at PLL Mode (see Table 2) Default: "00" (12.288MHz) MS0198-E-01 - 48 - 2003/5 ASAHI KASEI [AK4538] Addr 05H Register Name Mode Control 2 R/W Default D7 FS2 R/W 0 D6 FS1 R/W 0 D5 FS0 R/W 0 D4 HPRM R/W 0 D3 HPLM R/W 0 D2 HPM R/W 0 D1 LOOP R/W 0 D0 SPPS R/W 0 SPPS: Speaker-amp Power-Save-Mode 0: Power Save Mode (Default) 1: Normal Operation When the SPPS bit = "1", the Speaker-amp is in power-save-mode and the SPP pin becomes Hi-z and SPN pin is set to HVDD/2 voltage. When the PMSPK bit = "1", this bit is valid. After the PDN pin changes from "L" to "H", the PMSPK bit is "0", which powers down Speaker-amp LOOP: Loopback ON/OFF 0: OFF (Default) 1: ON When this bit is "1", the ADC output is passed to the DAC input internally. The external input data to DAC is ignored. HPM: Mono output select of Headphone 0: Stereo (Default) 1: Mono. When the HPM bit = "1", (L+R)/2 signals are output to Lch and Rch of the Headphone-amp. HPLM: Lch of HP-Amp output control 0: Enable output from Rch of Headphone-amp (Default) 1: Lch mono output of Headphone-amp. The PMHPR bit can be powered down at this time. HPRM: Rch of HP-Amp output control 0: Enable output from Lch of Headphone-amp (Default) 1: Rch mono output of Headphone-amp. The PMHPL bit can be powered down at this time. Output Channel Lch Rch L R L R (L+R)/2 (L+R)/2 (L+R)/2 (L+R)/2 Register bit PMHPL PMHPR HPL HPR 1 1 0 0 1 0 0 1 0 1 1 0 1 1 0 0 1 0 0 1 0 1 1 0 Table 25. Output control for Headphone-amp HPM 0 0 0 1 1 1 HPLM 0 1 0 0 1 0 HPRM 0 0 1 0 0 1 FS2-0: Sampling frequency modes (see Table 3 and Table 7) Default: "000" (fs=44.1kHz) MS0198-E-01 - 49 - 2003/5 ASAHI KASEI [AK4538] Addr 06H Register Name DAC Control R/W Default D7 TM1 R/W 0 D6 TM0 R/W 0 D5 SMUTE R/W 0 D4 DATTC R/W 1 D3 BST1 R/W 0 D2 BST0 R/W 0 D1 DEM1 R/W 0 D0 DEM0 R/W 1 DEM1-0: De-emphases response (see Table 19) Default is "01" (OFF). BST1-0: Select Low Frequency Boost Function (see Table 20) Default is "00" (OFF). DATTC: DAC Digital Attenuator Control Mode Select 0: ATTL7-0 and ATTR7-0 bits control the attenuator level of Lch and Rch respectively. 1: ATTL7-0 bits control both Lch and Rch at same time. (Default) ATTR7-0 bits are not changed when the ATTL7-0 bits are written. SMUTE: Soft Mute Control 0: Normal Operation (Default) 1: DAC outputs soft-muted Soft mute operation is independent of digital attenuator and is performed in the digital domain. TM1-0: Soft Mute Time Select (see Table 26) Default: "00" (1024/fs) TM1 0 0 1 1 TM0 Cycle 0 1024/fs Default 1 512/fs 0 256/fs 1 128/fs Table 26. Soft Mute Time Setting MS0198-E-01 - 50 - 2003/5 ASAHI KASEI [AK4538] Addr 07H Register Name MIC/HP Control R/W Default D7 0 RD 0 D6 0 RD 0 D5 AUXAD R/W 0 D4 MPWRE R/W 0 D3 MPWRI R/W 0 D2 MICAD R/W 0 D1 MSEL R/W 0 D0 MGAIN R/W 1 MGAIN: 1st Mic-amp Gain control 0: 0dB 1: 20dB (Default) MSEL: Microphone select 0: Internal Mic (Default) 1: External Mic MICAD: Switch Control from Mic In to ADC. 0: OFF (Default) 1: ON MPWRI: Power Supply Control for Internal Microphone 0: OFF (Default) 1: ON MPWRE: Power Supply for External Microphone 0: OFF (Default) 1: ON AUXAD: Switch Control from AUX IN to ADC. 0: OFF (Default) 1: ON MS0198-E-01 - 51 - 2003/5 ASAHI KASEI [AK4538] Addr 08H Register Name Timer Select R/W Default D7 0 RD 0 D6 ROTM R/W 0 D5 ZTM1 R/W 0 D4 ZTM0 R/W 0 D3 WTM1 R/W 0 D2 WTM0 R/W 0 D1 LTM1 R/W 0 D0 LTM0 R/W 0 LTM1-0: ALC1 limiter operation period at zero crossing disable (ZELM bit = "1") (see Table 27) The IPGA value is changed immediately. When the IPGA value is changed continuously, the change is done by the period specified by the LTM1-0 bits. Default is "00" (0.5/fs). LTM1 0 0 1 1 ALC1 Limiter Operation Period 8kHz 16kHz 44.1kHz Default 0 0.5/fs 63s 31s 11s 1 1/fs 125s 63s 23s 0 2/fs 250s 125s 45s 1 4/fs 500s 250s 91s Table 27. ALC1 Limiter Operation Period at zero crossing disable (ZELM bit = "1") LTM0 WTM1-0: ALC1 Recovery Waiting Period (see Table 28) A period of recovery operation when any limiter operation does not occur during the ALC1 operation. Default is "00" (128/fs). ZTM1 0 0 1 1 ZTM0 0 1 0 1 ALC1 Recovery Operation Waiting Period 8kHz 16kHz 44.1kHz 128/fs 16ms 8ms 2.9ms 256/fs 32ms 16ms 5.8ms 512/fs 64ms 32ms 11.6ms 1024/fs 128ms 64ms 23.2ms Table 28. ALC1 Recovery Operation Waiting Period Default ZTM1-0: Zero crossing timeout for the write operation by the P, ALC1 recovery, and zero crossing enable (ZELM bit = "0") of the ALC1 operation. (see Table 29) When the IPGA of each L/R channels perform zero crossing or timeout independently, the IPGA value is changed by the P WRITE operation, ALC1 recovery operation or ALC1 limiter operation (ZELM bit = "0"). Default is "00" (128/fs). ZTM1 0 0 1 1 ZTM0 0 1 0 1 Zero Crossing Timeout Period 8kHz 16kHz 44.1kHz 128/fs 16ms 8ms 2.9ms 256/fs 32ms 16ms 5.8ms 512/fs 64ms 32ms 11.6ms 1024/fs 128ms 64ms 23.2ms Table 29. Zero Crossing Timeout Period Default ROTM: Period time for ALC2 Recovery operation 0: 2048/fs (Default) 1: 512/fs MS0198-E-01 - 52 - 2003/5 ASAHI KASEI [AK4538] Addr 09H Register Name ALC Mode Control 1 R/W Default D7 0 RD 0 D6 ALC2 R/W 1 D5 ALC1 R/W 0 D4 ZELM R/W 0 D3 LMAT1 R/W 0 D2 LMAT0 R/W 0 D1 RATT R/W 0 D0 LMTH R/W 0 LMTH: ALC1 Limiter Detection Level / Recovery Waiting Counter Reset Level (see Table 30) The ALC1 limiter detection level and the ALC1 recovery counter reset level may be offset by about 2dB. Default is "0". LMTH 0 1 ALC1 Limiter Detection Level ALC1 Recovery Waiting Counter Reset Level ADC Input -6.0dBFS -6.0dBFS > ADC Input -8.0dBFS ADC Input -4.0dBFS -4.0dBFS > ADC Input -6.0dBFS Table 30. ALC1 Limiter Detection Level / Recovery Waiting Counter Reset Level Default RATT: ALC1 Recovery GAIN Step (see Table 31) During the ALC1 recovery operation, the number of steps changed from the current IPGA value is set. For example, when the current IPGA value is 30H and RATT bit = "1" is set, the IPGA changes to 32H by the ALC1 recovery operation and the output signal level is gained up by 1dB (=0.5dB x 2). When the IPGA value exceeds the reference level (REF6-0 bits), the IPGA value does not increase. RATT GAIN STEP 0 1 Default 1 2 Table 31. ALC1 Recovery Gain Step Setting LMAT1-0: ALC1 Limiter ATT Step (see Table 32) During the ALC1 limiter operation, when either Lch or Rch exceeds the ALC1 limiter detection level set by LMTH, the number of steps attenuated from the current IPGA value is set. For example, when the current IPGA value is 47H and the LMAT1-0 bits = "11", the IPGA transition to 43H when the ALC1 limiter operation starts, resulting in the input signal level being attenuated by 2dB (=0.5dB x 4). When the attenuation value exceeds IPGA = "00" (-8dB), it clips to "00". LMAT1 LMAT0 ATT STEP 0 0 1 Default 0 1 2 1 0 3 1 1 4 Table 32. ALC1 Limiter ATT Step Setting ZELM: Enable zero crossing detection at ALC1 Limiter operation 0: Enable (Default) 1: Disable When the ZELM bit = "0", the IPGA of each L/R channel perform a zero crossing or timeout independently and the IPGA value is changed by the ALC1 operation. The zero crossing timeout is the same as the ALC1 recovery operation. When the ZELM bit = "1", the IPGA value is changed immediately. ALC1: ALC1 Enable Flag 0: ALC1 Disable (Default) 1: ALC1 Enable ALC2: ALC2 Enable Flag 0: ALC2 Disable 1: ALC2 Enable (Default) MS0198-E-01 - 53 - 2003/5 ASAHI KASEI [AK4538] Addr 0AH Register Name ALC Mode Control 2 R/W Default D7 0 RD 0 D6 REF6 R/W 0 D5 REF5 R/W 1 D4 REF4 R/W 1 D3 REF3 R/W 0 D2 REF2 R/W 1 D1 REF1 R/W 1 D0 REF0 R/W 0 REF6-0: Reference value at ALC1 Recovery Operation (see Table 33) During the ALC1 recovery operation, if the IPGA value exceeds the setting reference value by gain operation, then the IPGA does not become larger than the reference value. For example, when REF7-0 = "30H", RATT = 2step, IPGA = 2FH, even if the input signal does not exceed the "ALC1 Recovery Waiting Counter Reset Level", the IPGA does not change to 2FH + 2step = 31H, and keeps 30H. Default is "36H". DATA (HEX) GAIN (dB) STEP 47 +27.5 46 +27.0 45 +26.5 : : 36 +19.0 Default : : 10 +0.0 : : 0.5dB 06 -5.0 05 -5.5 04 -6.0 03 -6.5 02 -7.0 01 -7.5 00 -8.0 Table 33. Setting Reference Value at ALC1 Recovery Operation MS0198-E-01 - 54 - 2003/5 ASAHI KASEI [AK4538] Addr 0BH Register Name Input PGA Control R/W Default D7 0 RD 0 D6 IPGA6 R/W 0 D5 IPGA5 R/W 0 D4 IPGA4 R/W 1 D3 IPGA3 R/W 0 D2 IPGA2 R/W 0 D1 IPGA1 R/W 0 D0 IPGA0 R/W 0 IPGA6-0: Input Analog PGA (see Table 34) Default: "10H" (0dB) When IPGA gain is changed, IPGA6-0 bits should be written while PMMIC bit is "1" and ALC1 bit is "0". IPGA gain is reset when PMMIC bit is "0", and then IPGA operation starts from the default value when PMMIC is changed to "1". When ALC1 bit is changed from "1" to "0", IPGA holds the last gain value set by ALC1 operation. When IPGA6-0 bits are read, the register values written by the last write operation are read out regardless the actual gain. DATA (HEX) 47 46 45 : 36 : 10 : 06 05 04 03 02 01 00 GAIN (dB) STEP +27.5 +27.0 +26.5 : +19.0 : +0.0 : 0.5dB -5.0 -5.5 -6.0 -6.5 -7.0 -7.5 -8.0 Table 34. Input Gain Setting Default Addr 0CH 0DH Register Name Lch Digital ATT Control Rch Digital ATT Control R/W Default D7 ATTL7 ATTR7 R/W 0 D6 ATTL6 ATTR6 R/W 0 D5 ATTL5 ATTR5 R/W 0 D4 ATTL4 ATTR4 R/W 0 D3 ATTL3 ATTR3 R/W 0 D2 ATTL2 ATTR2 R/W 0 D1 ATTL1 ATTR1 R/W 0 D0 ATTL0 ATTR0 R/W 0 ATTL/R7-0: Digital ATT Output Control (see Table 21) Default: "00H" (0dB) MS0198-E-01 - 55 - 2003/5 ASAHI KASEI [AK4538] Addr 0EH Register Name Volume Control R/W Default D7 ATTM RD 0 D6 ATTS2 R/W 1 D5 ATTS1 R/W 0 D4 ATTS0 R/W 1 D3 GN3 R/W 0 D2 GN2 R/W 1 D1 GN1 R/W 1 D0 GN0 R/W 1 GN3-0: Volume of AUX In (see Table 22) ATTS2-0: Attenuator select of signal from MIC IN to Stereo Mixer. (See Table 15) ATTM: Attenuator control for signal from MIC IN to Mono Mixer 0: OFF. 0dB (Default) 1: ON. -4dB Addr 0FH Register Name Status R/W Default D7 0 RD 0 D6 0 RD 0 D5 0 RD 0 D4 0 RD 0 D3 0 RD 0 D2 0 RD 0 D1 0 RD 0 D0 DTMIC RD 0 DTMIC: Microphone Detection Result 0: Microphone is not detected.(Default) 1: Microphone is detected. MS0198-E-01 - 56 - 2003/5 ASAHI KASEI [AK4538] SYSTEM DESIGN (52pin QFN) Figure 46 shows the system connection diagram for the 52-pin QFN version of the AK4538. An evaluation board [AKD4538] is available which demonstrates the optimum layout, power supply arrangements and measurement results. 1 R 52 1 NC 1 MICOUT 2 MDT 1 3 EXT 2.2k 4 MPE 2.2k 5 MPI 1 6 INT 0.1 0.1 9 AVDD 10 PVDD 10 0.1 11 PVSS 10k 4.7n 12 VCOC CSN/CAD1 CDTI/SDA 13 NC CAD0 PDN CCLK/SCL DVSS 29 0.1 DVDD 28 NC 27 MCKO CDTO SDTO LRCK BICK SDTI I2C NC 10 10 XTI/MCKI 31 XTO 30 C C 7 VCOM 8 AVSS 10 SPN 34 HVDD 35 8 HVSS 36 0.1 10 Analog Supply 2.4 ~ 3.6V HPR 37 51 AIN 50 BEEPL R 49 BEEPR 1 R 48 BEEPM 47 AUXIN+ 46 AUXIN45 MOUT+ 44 MOUT43 LOUT 42 ROUT 41 MOUT 40 MIN 10 0.22 1 MUTET 39 HPL 38 6.8 47 6.8 0.22 10 16 16 1 1 1 C C C C 1 2.2 Analog Supply 2.4 ~ 3.6V Top View SPP 33 M/S 32 14 15 16 17 18 19 20 21 22 23 24 25 26 Reset DSP and uP Notes: - AVSS, DVSS, PVSS and HVSS of the AK4538 should be distributed separately from the ground of external controllers. - Values of R and C in Figure 46 should depend on system. - All input pins should not be left floating. Figure 46. Typical Connection Diagram MS0198-E-01 - 57 - 2003/5 ASAHI KASEI [AK4538] 1. Grounding and Power Supply Decoupling The AK4538 requires careful attention to power supply and grounding arrangements. AVDD, DVDD, PVDD and HVDD are usually supplied from the system's analog supply. If AVDD, DVDD, PVDD and HVDD are supplied separately, the correct power up sequence should be observed. AVSS, DVSS, PVSS and HVSS of the AK4538 should be connected to the analog ground plane. System analog ground and digital ground should be connected together near to where the supplies are brought onto the printed circuit board. Decoupling capacitors should be as near to the AK4538 as possible, with the small value ceramic capacitor being the nearest. 2. Voltage Reference VCOM is a signal ground of this chip. A 2.2F electrolytic capacitor in parallel with a 0.1F ceramic capacitor attached to the VCOM pin eliminates the effects of high frequency noise. No load current may be drawn from the VCOM pin. All signals, especially clocks, should be kept away from the VREF and VCOM pins in order to avoid unwanted coupling into the AK4538. 3. Analog Inputs The Mic and Beep inputs are single-ended. The input signal range scales with nominally at 0.06 x AVDD Vpp for the Mic input and 0.6 x AVDD Vpp for the Beep input, centered around the internal common voltage (0.45 x AVDD). Usually the input signal is AC coupled using a capacitor. The cut-off frequency is fc = (1/2RC). The AK4538 can accept input voltages from AVSS to AVDD. 4. Analog Outputs The input data format for the DAC is 2's complement. The output voltage is a positive full scale for 7FFFH(@16bit) and a negative full scale for 8000H(@16bit). Mono output from the MOUT2 pin and Mono Line Output from the MOUT+ and MOUT- pins are centered at 0.45 x AVDD. The Headphone-Amp and Speaker-Amp outputs are centered at HVDD/2. MS0198-E-01 - 58 - 2003/5 ASAHI KASEI [AK4538] CONTOROL SEQUENCE n Power up Upon power-up, bring the PDN pin = "L". Initialize the internal registers to default values after the PDN pin = "H". Set the following registers to establish the initial condition. Pow er Supply (2) E xam p le : A u d i o I / F F o r m a t : I2 S B ICK frequency at M a s ter M o d e : 64fs Input M a s t e r C lo c k S e le c t a t P L L M o d e : 1 1 . 2 8 9 6 M H z PDN pin (3) (1 ) P o w e r S u p p ly PMVCM bit (Addr:00H, D7) (4) (2 ) P D N p in = "L " "H " (3 ) A d d r:0 0 H , D a t a 8 0 H MOUT2 bit (Addr:02H, D0) ALCS bit (Addr:02H, D1) (5) (4 ) A d d r:0 2 H , D a t a 0 3 H HPL/R bits (Addr:03H, D1-0) (5 ) A d d r:0 3 H , D a t a 8 0 H DAHS bit (Addr:03H, D7) (6) (6 ) A d d r:0 4 H , D a t a 4 2 H DIF1-0 bits (Addr:04H, D1-0) 10 0 00 XX X XX BF bit (Addr:04H, D2) PLL1-0 bits (Addr:04H, D7-6) Figure 47. Power Up Sequence MS0198-E-01 - 59 - 2003/5 ASAHI KASEI [AK4538] n Clock Set up When ADC, DAC, ALC1 and ALC2 are used, the clocks (MCLK, BICK and LRCK) must be supplied. 1. When X'tal is used in PLL mode. (Slave mode) MCKPD bit (Addr:01H, D7) (1) E xam p le : A u d io I/F F o r m a t : I 2 S B ICK frequency at M a ster M o d e : 64fs I n p u t M a s t e r C lo c k S e le c t a t P L L M o d e : 1 1 .2 8 9 6 M H z O utp u t M a s t e r C lo c k F re q ue n c y : 6 4 f s PMXTL bit (Addr:01H, D6) 20ms(typ) (2) 40ms(max) PMPLL bit (Addr:01H, D5) (1 ) A d d r : 0 1 H , D a t a : 4 0 H (2 ) A d d r : 0 1 H , D a t a : 6 0 H MCKO bit (Addr:04H, D3) (3) (4) (3 ) A d d r : 0 4 H , D a t a 4 A H MCKO pin (5) Output (4 ) M C K O o u t p u t s t a r t s BICK, LRCK (Slave Mode) Input (5 ) B I C K a n d L R C K i n p u t s t a r t (6) PS1-0 bits (Addr:04H, D5-4) 00 XX (6 ) A d d r : 0 4 H , D a t a 6 A H Figure 48. Clock Set Up Sequence(1) MS0198-E-01 - 60 - 2003/5 ASAHI KASEI [AK4538] 2. When X'tal is used in PLL mode. (Master mode) MCKPD bit (Addr:01H, D7) (1) E xam p le : A u d io I/F F o r m a t : I 2 S B ICK frequency at M a ster M o d e : 64fs I n p u t M a s t e r C lo c k S e le c t a t P L L M o d e : 1 1 .2 8 9 6 M H z O utp u t M a s t e r C lo c k F re q ue n c y : 6 4 f s PMXTL bit (Addr:01H, D6) 20ms(typ) (2) (1 ) A d d r : 0 1 H , D a t a : 4 0 H 40msec(max) PMPLL bit (Addr:01H, D5) (2 ) A d d r : 0 1 H , D a t a : 6 0 H MCKO bit (Addr:04H, D3) (3) (3 ) A d d r : 0 4 H , D a t a 6 A H PS1-0 bits (Addr:04H, D5-4) 00 (4) XX Output Output (4 ) M C K O , B I C K a n d L R C K o u t p u t s t a r t s MCKO pin BICK, LRCK (Master Mode) Figure 49. Clock Set Up Sequence(2) MS0198-E-01 - 61 - 2003/5 ASAHI KASEI [AK4538] 3. When an external clock is used in PLL mode. (Slave mode) E xam p le : A u d io I/F F o r m a t : I 2 S B ICK frequency at Master Mode : 64fs Inp u t M a s t e r C lo c k S e lect at P L L M o d e : 1 1 . 2 8 9 6 M H z O utp u t M a s t e r C lo c k F r e q u e n c y : 6 4 f s MCKPD bit (Addr:01H, D7) (1) External MCLK PMPLL bit (Addr:01H, D5) (2) Input (3) ( 1 ) A d d r :0 1 H , D a t a : 0 0 H (2) Input external M C L K 40ms(max) MCKO bit (Addr:04H, D3) (4) ( 3 ) A d d r :0 1 H , Data 2 0 H MCKO pin BICK, LRCK (Slave Mode) (5) ( 4 ) A d d r :0 4 H , D a t a 4 A H Output (5) MCKO output starts (6) (7) Input ( 6 ) B I C K a n d L R C K inp u t s t a r t PS1-0 bits (Addr:04H, D5-4) 00 XX ( 7 ) A d d r :0 4 H , D a t a 6 A H Figure 50. Clock Set Up Sequence(3) MS0198-E-01 - 62 - 2003/5 ASAHI KASEI [AK4538] 4. When an external clock is used in PLL mode. (Master mode) MCKPD bit (Addr:01H, D7) (1) Exam p le : Audio I/F Format : I 2 S BICK frequency at Master Mode : 64fs Input Master Clo c k S e lect at PLL Mode : 11.2896MHz O utput Master Clock Frequency : 64fs External MCLK PMPLL bit (Addr:01H, D5) (2) (3) 40ms(max) Input (1) Addr:0 1 H , Data:00H (2) Input external MCLK MCKO bit (Addr:04H, D3) (4) (3) Addr:0 1 H , Data 20H PS1-0 bits (Addr:04H, D5-4) 00 (5) XX Output Output (4) Addr:0 4 H , Data 6AH (5) MCKO, BICK and LRCK output starts MCKO pin BICK, LRCK (Master Mode) Figure 51. Clock Set Up Sequence(4) 5. External clock mode MCKPD bit (Addr:01H, D7) (2) (1) Exam p le : Audio I/F Format : I 2 S BICK frequency at Master Mode : 64fs Input Master Clock Frequency : 256fs O utput Master Clock Frequency : 64fs FS1-0 bits (Addr:05H, D6-5) 00 (3) XX (1) Addr:01H, Data:00H External MCLK BICK, LRCK (Slave Mode) Input Input Output (2) A d d r:05H, Data 00H (4) (3) Input external MCLK BICK, LRCK (Master Mode) (5) (4) Input BICK a n d L R C K ( S lave) (5) BICK and LRCK output(Master) Figure 52. Clock Set Up Sequence(5) MS0198-E-01 - 63 - 2003/5 ASAHI KASEI [AK4538] n MIC Input Recording FS2-0 bits (Addr:05H, D7-5) Example : 000 (1) XXX XX1XX (2) MIC Control (Addr:07H, D2-0) 00001 XXH (3) X'tal and PLL are used. Sampling Frequency : 8kHz Mic Select : Internal Mic Pre Mic AMP : +20dB MIC Power On ALC1 setting : Refer to Figure 9 ALC2 bit = "1"(default) ALC1 Control 1 (Addr:08H) 00H 47H (4) (1) Addr:05H, Data:E0H ALC1 Control 2 (Addr:0AH) XXH (2) Addr:07H, Data:0DH ALC1 Control 3 (Addr:09H) (3) Addr:08H, Data:00H XXH (5) 61H or 21H (4) Addr:0AH, Data:47H ALC1 State PMADC bit (Addr:00H, D0) ALC1 Disable ALC1 Enable ALC1 Disable (5) Addr:09H, Data:61H (6) (7) 2081 / fs (6) Addr:00H, Data 83H PMMIC bit (Addr:00H, D1) Recording ADC Internal State Power Down Initialize Normal State Power Down (7) Addr:00H, Data 80H Figure 53. MIC Input Recording Sequence MS0198-E-01 - 64 - 2003/5 ASAHI KASEI [AK4538] n Headphone-amp Output E x a m p le : X 't a l a n d P L L a r e u s e d . S a m p ling Frequency : 44.1kH z D A T T C b it = " 1 " ( d e f a u lt) D igital A ttenuato r L e v e l : -8 d B B a s s B o o s t L e v e l : M iddle D e -e m p h a s e s r e s p o n s e : O F F S o ft M ute Tim e : 1 0 2 4 / f s FS2-0 bits (Addr:05H, D7-5) 000 (1) XXX 00 (2) (1) A d d r:05H, Data:00H BST1-0 bits (Addr:06H, D3-2) XX (8) 00 (2) A d d r : 0 6 H , D a t a 1 9 H ATTL7-0 bits (Addr:0CH 0DH, D7-0) 0000000 (3) XXXXXXX (3 ) A d d r : 0 C H , D a t a 1 0 H (4) A d d r:01H, Data 67H PMDAC bit (Addr:01H, D0) (4) (7) ( 5 ) R e le a s e e x t e r n a l M u t e PMHPL/R bits (Addr:01H, D2-1) P la y b a c k HPL/R pins (5) Normal Output (6) ( 6 ) E n a b le e x t e r n a l M u t e (7) A d d r : 0 1 H , D a t a 6 0 H External Mute (8) A d d r : 0 6 H , D a t a 1 1 H Figure 54. Headphone-Amp Output Sequence MS0198-E-01 - 65 - 2003/5 ASAHI KASEI [AK4538] n Speaker-amp Output FS2-0 bits (Addr:05H, D7-5) 000 (1) XXX E x a m p le : ALC2 bit (Addr:09H, D6 0 (2) X XXXXXXX (3) X 't a l a n d P L L a r e u s e d . S a m p li n g F r e q u e n c y : 4 8 k H z D A T T C b it = " 1 " ( d e f a u lt ) D igita l A t t e n u a t o r L e v e l : 0 d B A L C 1 : D isable A L C 2 : D isable ATTL7-0 bits (Addr:0CH 0DH, D7-0) 0000000 (1 ) A d d r:0 5 H , D a t a 6 0 H PMDAC bit (Addr:01H, D0) (4) (7) (2 ) A d d r:0 9 H , D a t a 0 0 H PMSPK bit (Addr:01H, D3) (3 ) A d d r:0 C H , D a t a 0 0 H (4 ) A d d r:0 1 H , D a t a 6 9 H SPPS bit (Addr:05H, D0) (5) (6) (5 ) A d d r:0 5 H , D a t a 6 1 H P layb a c k SPP pin SPN pin Hi-Z Hi-Z HVDD/2 Normal Output Normal Output Hi-Z HVDD/2 Hi-Z (6 ) A d d r:0 5 H , D a t a 6 0 H (7 ) A d d r:0 1 H , D a t a 6 0 H Figure 55. Speaker-Amp Output Sequence MS0198-E-01 - 66 - 2003/5 ASAHI KASEI [AK4538] n Stop of Clock MCLK can be stopped when PMMIC=PMADC=PMDAC=PMSPK= "0". 1. When X'tal is used in PLL mode MCKO bit (Addr:03H, D4) (1) E xam p le : A u d i o I / F F o r m a t : I2 S B I C K f r e q u e n c y a t M aster M o d e : 64fs Input M a s t e r C lo c k S e le c t a t P L L M o d e : 1 1 . 2 8 9 6 M H z O utput M a s t e r C lo c k Frequency : 64fs PMXTL bit (Addr:01H, D6) (2) (1) Addr:04H, Data:62H PMPLL bit (Addr:01H, D5) (3) (2) Addr:01H, Data:00H MCKPD bit (Addr:01H, D7) (3) Addr:01H, Data 80H Figure 56. Stop of Clock Sequence(1) 2. When an external clock is used in PLL mode E x a m p le : MCKO bit (Addr:03H, D4) (1) (2) A u d io I/F : I 2 S BICK frequency at Master Mode : 64fs Input Master Clock Select at PLL Mode : 11.2896MHz Output Master Clock Frequency : 64fs PMPLL bit (Addr:01H, D5) (1) Addr:04H, Data:62H MCKPD bit (Addr:01H, D7) (3) (2) Addr:01H, Data:80H (3) Stop external clock External MCLK Input Figure 57. Stop of Clock Sequence(2) MS0198-E-01 - 67 - 2003/5 ASAHI KASEI [AK4538] E x a m p le : MCKO bit (Addr:03H, D4) (1) (2) A u d io I/F : I 2 S BICK frequency at Master Mode : 64fs Input Master Clock Select at PLL Mode : 11.2896MHz Output Master Clock Frequency : 64fs PMPLL bit (Addr:01H, D5) (1) Addr:04H, Data:62H MCKPD bit (Addr:01H, D7) (3) (2) Addr:01H, Data:80H (3) Stop external clock External MCLK Input Figure 58. Stop of Clock Sequence(3) n Power down Power down VCOM(PMVCM= "1" "0") after all blocks except VCOM are powered down and MCLK stops. The AK4538 is also powered-down by PDN pin = "L". When PDN pin = "L", the registers are initialized. MS0198-E-01 - 68 - 2003/5 ASAHI KASEI [AK4538] PACKAGE 52pin QFN (Unit: mm) 7.2 0.20 7.0 0.10 52 1 40 39 39 0.20 + 0.10 - 0.20 0.60 + 0.10 - 0.30 40 30 0. 52 1 10 0. 4 - C0.6 7.2 0.20 7.0 0.10 45 45 13 27 27 13 14 26 0.78 + 0.17 - 0.28 26 0.80 + 0.20 - 0.00 14 0.40 0.21 0.05 0.18 0.05 0.05 M 0.05 Note) The part of black at four corners on reverse side must not be soldered and must be open. n Material & Lead finish Package molding compound: Lead frame material: Lead frame surface treatment: Epoxy Cu Solder plate (Pb free) MS0198-E-01 - 69 - 0.02 + 0.03 - 0.02 2003/5 ASAHI KASEI [AK4538] MARKING n 52pin QFN AKM AK4538VN XXXXXXX 1 XXXXXXX : Date code identifier (7 digits) IMPORTANT NOTICE * These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. * AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. * Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. * AKM products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of AKM. As used here: a. A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. b. A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. * It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification. MS0198-E-01 - 70 - 2003/5 |
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